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https://github.com/YosysHQ/yosys
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Migrate build system to CMake
See #5895 for details. This commit does not include CI or documentation changes.
This commit is contained in:
Catherine
parent
9d0cdb8551
commit
cad5353a2a
208 changed files with 5285 additions and 2294 deletions
1
techlibs/quicklogic/.gitignore
vendored
1
techlibs/quicklogic/.gitignore
vendored
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@ -1 +0,0 @@
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/*_pm.h
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104
techlibs/quicklogic/CMakeLists.txt
Normal file
104
techlibs/quicklogic/CMakeLists.txt
Normal file
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@ -0,0 +1,104 @@
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yosys_pass(ql_bram_merge
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ql_bram_merge.cc
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)
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yosys_pass(ql_bram_types
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ql_bram_types.cc
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)
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pmgen_command(ql_dsp_macc
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ql_dsp_macc.pmg
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)
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yosys_pass(ql_dsp_macc
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ql_dsp_macc.cc
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${PMGEN_ql_dsp_macc_OUTPUT}
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)
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yosys_pass(ql_dsp_simd
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ql_dsp_simd.cc
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)
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yosys_pass(ql_dsp_io_regs
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ql_dsp_io_regs.cc
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)
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yosys_pass(ql_ioff
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ql_ioff.cc
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)
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add_custom_command(
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DEPENDS qlf_k6n10f/generate_bram_types_sim.py
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# yosys_pass(DATA_FILES) expects the files to be in the source directory
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OUTPUT ${CMAKE_CURRENT_SOURCE_DIR}/qlf_k6n10f/bram_types_sim.v
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COMMAND ${Python3_EXECUTABLE} qlf_k6n10f/generate_bram_types_sim.py qlf_k6n10f/bram_types_sim.v
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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VERBATIM
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)
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yosys_pass(synth_quicklogic
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synth_quicklogic.cc
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REQUIRES
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abc9
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alumacc
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autoname
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blackbox
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check
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chtype
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clean
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clkbufmap
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deminout
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dfflegalize
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flatten
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fsm
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hierarchy
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iopadmap
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memory
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memory_libmap
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memory_map
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muxcover
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opt
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opt_clean
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opt_expr
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opt_lut
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peepopt
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pmuxtree
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proc
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ql_bram_merge
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ql_bram_types
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ql_dsp_io_regs
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ql_dsp_macc
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ql_dsp_simd
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ql_ioff
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read_verilog
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setundef
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share
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shregmap
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stat
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techmap
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tribuf
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wreduce
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write_blif
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write_verilog
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DATA_DIR
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quicklogic
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DATA_FILES
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common/cells_sim.v
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pp3/ffs_map.v
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pp3/lut_map.v
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pp3/latches_map.v
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pp3/cells_map.v
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pp3/cells_sim.v
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pp3/abc9_model.v
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pp3/abc9_map.v
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pp3/abc9_unmap.v
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qlf_k6n10f/arith_map.v
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qlf_k6n10f/libmap_brams.txt
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qlf_k6n10f/libmap_brams_map.v
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qlf_k6n10f/brams_map.v
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qlf_k6n10f/brams_sim.v
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qlf_k6n10f/bram_types_sim.v
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qlf_k6n10f/cells_sim.v
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qlf_k6n10f/ffs_map.v
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qlf_k6n10f/dsp_sim.v
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qlf_k6n10f/dsp_map.v
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qlf_k6n10f/dsp_final_map.v
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qlf_k6n10f/TDP18K_FIFO.v
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qlf_k6n10f/ufifo_ctl.v
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qlf_k6n10f/sram1024x18_mem.v
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)
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@ -1,44 +0,0 @@
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techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ $@
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OBJS += techlibs/quicklogic/synth_quicklogic.o
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OBJS += techlibs/quicklogic/ql_bram_merge.o
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OBJS += techlibs/quicklogic/ql_bram_types.o
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OBJS += techlibs/quicklogic/ql_dsp_simd.o
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OBJS += techlibs/quicklogic/ql_dsp_io_regs.o
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OBJS += techlibs/quicklogic/ql_ioff.o
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# --------------------------------------
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OBJS += techlibs/quicklogic/ql_dsp_macc.o
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GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v
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techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h
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$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h))
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# --------------------------------------
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$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v))
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$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v))
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$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v))
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$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v))
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