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Migrate build system to CMake

See #5895 for details.

This commit does not include CI or documentation changes.
This commit is contained in:
Catherine 2026-05-12 05:33:04 +00:00
parent 9d0cdb8551
commit cad5353a2a
208 changed files with 5285 additions and 2294 deletions

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@ -0,0 +1,76 @@
pmgen_command(microchip_dsp
microchip_dsp.pmg
)
pmgen_command(microchip_dsp_cascade
microchip_dsp_cascade.pmg
)
pmgen_command(microchip_dsp_CREG
microchip_dsp_CREG.pmg
)
yosys_pass(microchip_dffopt
microchip_dffopt.cc
)
yosys_pass(microchip_dsp
microchip_dsp.cc
${PMGEN_microchip_dsp_OUTPUT}
${PMGEN_microchip_dsp_cascade_OUTPUT}
${PMGEN_microchip_dsp_CREG_OUTPUT}
)
yosys_pass(synth_microchip
synth_microchip.cc
REQUIRES
abc
alumacc
attrmap
blackbox
check
chtype
clean
clkbufmap
deminout
dfflegalize
extract_reduce
flatten
fsm
hierarchy
iopadmap
memory
memory_dff
memory_libmap
memory_map
microchip_dffopt
microchip_dsp
muxcover
opt
opt_clean
opt_expr
peepopt
proc
read_verilog
select
setattr
share
simplemap
stat
techmap
tribuf
wreduce
write_blif
write_edif
write_verilog
zinit
DATA_DIR
microchip
DATA_FILES
arith_map.v
cells_map.v
cells_sim.v
polarfire_dsp_map.v
brams_defs.vh
LSRAM_map.v
LSRAM.txt
uSRAM_map.v
uSRAM.txt
)

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@ -1,40 +0,0 @@
# ISC License
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
OBJS += techlibs/microchip/synth_microchip.o
OBJS += techlibs/microchip/microchip_dffopt.o
$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/polarfire_dsp_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))
OBJS += techlibs/microchip/microchip_dsp.o
GENFILES += techlibs/microchip/microchip_dsp_pm.h
GENFILES += techlibs/microchip/microchip_dsp_CREG_pm.h
GENFILES += techlibs/microchip/microchip_dsp_cascade_pm.h
techlibs/microchip/microchip_dsp.o: techlibs/microchip/microchip_dsp_pm.h techlibs/microchip/microchip_dsp_CREG_pm.h techlibs/microchip/microchip_dsp_cascade_pm.h
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_pm.h))
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_CREG_pm.h))
$(eval $(call add_extra_objs,techlibs/microchip/microchip_dsp_cascade_pm.h))