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intel_alm: enable M10K initialisation

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This commit is contained in:
Lofty 2023-05-25 17:48:48 +01:00
parent ec8d7b1c68
commit cac1bc6fbe
3 changed files with 10 additions and 6 deletions
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2
techlibs/intel_alm/common/bram_m10k.txt
View file

@ -1,5 +1,5 @@
bram $__MISTRAL_M10K
init 0 # TODO: Re-enable when I figure out how BRAM init works
init 1
abits 13 @D8192x1
dbits 1 @D8192x1
abits 12 @D4096x2

6
techlibs/intel_alm/common/bram_m10k_map.v
View file

@ -2,6 +2,8 @@
module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter INIT = 0;
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
@ -11,6 +13,6 @@ input [CFG_DBITS-1:0] A1DATA;
input A1EN, B1EN;
output reg [CFG_DBITS-1:0] B1DATA;
MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
MISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
endmodule
endmodule

8
techlibs/intel_alm/common/mem_sim.v
View file

@ -3,7 +3,7 @@
// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
// the memory the ALM uses to store the look-up table data for general usage,
// the memory the ALM uses to store the look-up table data for general usage,
// producing a 32 address by 20-bit block of memory. MLABs are spread out
// around the chip, so they can be placed near where they are needed, rather than
// being comparatively limited in placement for a deep but narrow memory such as
@ -43,7 +43,7 @@
// Quartus will pack external flops into the MLAB, but this is an assumption
// that needs testing.
// The vendor sim model outputs 'x for a very short period (a few
// The vendor sim model outputs 'x for a very short period (a few
// combinational delta cycles) after each write. This has been omitted from
// the following model because it's very difficult to trigger this in practice
// as clock cycles will be much longer than any potential blip of 'x, so the
@ -110,6 +110,8 @@ endmodule
module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter INIT = 0;
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
@ -119,7 +121,7 @@ input [CFG_DBITS-1:0] A1DATA;
input A1EN, B1EN;
output reg [CFG_DBITS-1:0] B1DATA;
reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = INIT;
`ifdef cyclonev
specify