mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
Merge branch 'YosysHQ:main' into main
This commit is contained in:
Akash Levy
GitHub
commit
caaef5ac14
21 changed files with 432 additions and 137 deletions
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@ -18,12 +18,37 @@
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "backends/rtlil/rtlil_backend.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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std::optional<std::string> format(std::string fmt, const dict<IdString, Const> ¶meters)
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bool has_fmt_field(std::string fmt, std::string field_name)
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{
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auto it = fmt.begin();
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while (it != fmt.end()) {
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if (*it == '{') {
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it++;
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auto beg = it;
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while (it != fmt.end() && *it != '}') it++;
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if (it == fmt.end())
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return false;
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if (std::string(beg, it) == field_name)
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return true;
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}
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it++;
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}
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return false;
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}
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struct ContextData {
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std::string unused_outputs;
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};
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std::optional<std::string> format(std::string fmt, const dict<IdString, Const> ¶meters,
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const ContextData &context)
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{
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std::stringstream result;
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@ -38,13 +63,19 @@ std::optional<std::string> format(std::string fmt, const dict<IdString, Const> &
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return {};
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}
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auto id = RTLIL::escape_id(std::string(beg, it));
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if (!parameters.count(id)) {
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log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
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return {};
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}
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std::string param_name = {beg, it};
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RTLIL_BACKEND::dump_const(result, parameters.at(id));
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if (param_name == "%unused") {
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result << context.unused_outputs;
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} else {
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auto id = RTLIL::escape_id(std::string(beg, it));
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if (!parameters.count(id)) {
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log("Parameter %s referenced in format string '%s' not found\n", log_id(id), fmt.c_str());
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return {};
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}
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RTLIL_BACKEND::dump_const(result, parameters.at(id));
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}
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} else {
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result << *it;
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}
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@ -54,6 +85,45 @@ std::optional<std::string> format(std::string fmt, const dict<IdString, Const> &
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return {result.str()};
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}
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struct Chunk {
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IdString port;
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int base, len;
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Chunk(IdString id, int base, int len)
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: port(id), base(base), len(len) {}
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IdString format(Cell *cell)
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{
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if (len == cell->getPort(port).size())
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return port;
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else if (len == 1)
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return stringf("%s[%d]", port.c_str(), base);
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else
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return stringf("%s[%d:%d]", port.c_str(), base + len - 1, base);
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}
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SigSpec sample(Cell *cell)
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{
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return cell->getPort(port).extract(base, len);
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}
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};
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// Joins contiguous runs of bits into a 'Chunk'
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std::vector<Chunk> collect_chunks(std::vector<std::pair<IdString, int>> bits)
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{
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std::vector<Chunk> ret;
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std::sort(bits.begin(), bits.end());
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for (auto it = bits.begin(); it != bits.end();) {
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auto sep = it + 1;
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for (; sep != bits.end() &&
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sep->first == it->first &&
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sep->second == (sep - 1)->second + 1; sep++);
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ret.emplace_back(it->first, it->second, sep - it);
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it = sep;
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}
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return ret;
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}
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struct WrapcellPass : Pass {
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WrapcellPass() : Pass("wrapcell", "wrap individual cells into new modules") {}
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@ -68,6 +138,10 @@ struct WrapcellPass : Pass {
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log("parameter values as specified in curly brackets. If the named module already\n");
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log("exists, it is reused.\n");
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log("\n");
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log("If the template contains the special string '{%%unused}', the command tracks\n");
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log("unused output ports -- specialized wrapper modules will be generated per every\n");
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log("distinct set of unused port bits as appearing on any selected cell.\n");
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log("\n");
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log(" -setattr <attribute-name>\n");
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log(" set the given boolean attribute on each created wrapper module\n");
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log("\n");
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@ -114,35 +188,81 @@ struct WrapcellPass : Pass {
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CellTypes ct;
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ct.setup();
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bool tracking_unused = has_fmt_field(name_fmt, "%unused");
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for (auto module : d->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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std::optional<std::string> unescaped_name = format(name_fmt, cell->parameters);
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if (!unescaped_name)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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SigPool unused;
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IdString name = RTLIL::escape_id(unescaped_name.value());
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if (d->module(name)) {
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cell->type = name;
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cell->parameters.clear();
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continue;
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for (auto wire : module->wires())
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if (wire->has_attribute(ID::unused_bits)) {
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std::string str = wire->get_string_attribute(ID::unused_bits);
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for (auto it = str.begin(); it != str.end();) {
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auto sep = it;
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for (; sep != str.end() && *sep != ' '; sep++);
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unused.add(SigBit(wire, std::stoi(std::string(it, sep))));
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for (it = sep; it != str.end() && *it == ' '; it++);
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}
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}
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for (auto cell : module->selected_cells()) {
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Module *subm;
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Cell *subcell;
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if (!ct.cell_known(cell->type))
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log_error("Non-internal cell type '%s' on cell '%s' in module '%s' unsupported\n",
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log_id(cell->type), log_id(cell), log_id(module));
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Module *subm = d->addModule(name);
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Cell *subcell = subm->addCell("$1", cell->type);
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std::vector<std::pair<IdString, int>> unused_outputs, used_outputs;
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for (auto conn : cell->connections()) {
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Wire *w = subm->addWire(conn.first, conn.second.size());
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if (ct.cell_output(cell->type, w->name))
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w->port_output = true;
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else
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w->port_input = true;
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subcell->setPort(conn.first, w);
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if (ct.cell_output(cell->type, conn.first))
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for (int i = 0; i < conn.second.size(); i++) {
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if (tracking_unused && unused.check(conn.second[i]))
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unused_outputs.emplace_back(conn.first, i);
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else
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used_outputs.emplace_back(conn.first, i);
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}
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}
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ContextData context;
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if (!unused_outputs.empty()) {
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context.unused_outputs += "_unused";
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for (auto chunk : collect_chunks(unused_outputs))
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context.unused_outputs += "_" + RTLIL::unescape_id(chunk.format(cell));
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}
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std::optional<std::string> unescaped_name = format(name_fmt, cell->parameters, context);
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if (!unescaped_name)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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log_id(cell), log_id(module));
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IdString name = RTLIL::escape_id(unescaped_name.value());
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if (d->module(name))
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goto replace_cell;
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subm = d->addModule(name);
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subcell = subm->addCell("$1", cell->type);
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for (auto conn : cell->connections()) {
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if (ct.cell_output(cell->type, conn.first)) {
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// Insert marker bits as placehodlers which need to be replaced
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subcell->setPort(conn.first, SigSpec(RTLIL::Sm, conn.second.size()));
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} else {
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Wire *w = subm->addWire(conn.first, conn.second.size());
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w->port_input = true;
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subcell->setPort(conn.first, w);
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}
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}
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for (auto chunk : collect_chunks(used_outputs)) {
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Wire *w = subm->addWire(chunk.format(cell), chunk.len);
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w->port_output = true;
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subcell->connections_[chunk.port].replace(chunk.base, w);
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}
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for (auto chunk : collect_chunks(unused_outputs)) {
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Wire *w = subm->addWire(chunk.format(cell), chunk.len);
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subcell->connections_[chunk.port].replace(chunk.base, w);
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}
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subcell->parameters = cell->parameters;
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subm->fixup_ports();
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@ -150,7 +270,7 @@ struct WrapcellPass : Pass {
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if (rule.value_fmt.empty()) {
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subm->set_bool_attribute(rule.name);
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} else {
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std::optional<std::string> value = format(rule.value_fmt, cell->parameters);
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std::optional<std::string> value = format(rule.value_fmt, cell->parameters, context);
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if (!value)
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log_error("Formatting error when processing cell '%s' in module '%s'\n",
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@ -160,8 +280,20 @@ struct WrapcellPass : Pass {
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}
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}
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cell->type = name;
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replace_cell:
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cell->parameters.clear();
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dict<IdString, SigSpec> new_connections;
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for (auto conn : cell->connections())
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if (!ct.cell_output(cell->type, conn.first))
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new_connections[conn.first] = conn.second;
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for (auto chunk : collect_chunks(used_outputs))
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new_connections[chunk.format(cell)] = chunk.sample(cell);
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cell->type = name;
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cell->connections_ = new_connections;
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}
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}
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}
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@ -969,13 +969,10 @@ void prep_box(RTLIL::Design *design)
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if (it == module->attributes.end())
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continue;
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bool box = it->second.as_bool();
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module->attributes.erase(it);
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if (!box)
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continue;
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auto r = module->attributes.insert(ID::abc9_box_id);
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if (!r.second)
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continue;
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r.first->second = abc9_box_id++;
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if (module->get_bool_attribute(ID::abc9_flop)) {
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@ -1078,7 +1075,8 @@ void prep_box(RTLIL::Design *design)
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}
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ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
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ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
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bool has_model = module->get_bool_attribute(ID::whitebox) || !module->get_bool_attribute(ID::blackbox);
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ss << " " << (has_model ? "1" : "0");
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ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
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bool first = true;
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@ -1096,8 +1094,9 @@ void prep_box(RTLIL::Design *design)
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ss << std::endl;
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auto &t = timing.setup_module(module);
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if (t.comb.empty())
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if (t.comb.empty() && !outputs.empty() && !inputs.empty()) {
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log_error("Module '%s' with (* abc9_box *) has no timing (and thus no connectivity) information.\n", log_id(module));
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}
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for (const auto &o : outputs) {
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first = true;
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@ -19,10 +19,29 @@
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules)
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{
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std::set<Module *> modules_set(modules.begin(), modules.end());
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TopoSort<Module*> sort;
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for (auto m : modules) {
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sort.node(m);
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for (auto cell : m->cells()) {
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Module *submodule = design->module(cell->type);
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if (modules_set.count(submodule))
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sort.edge(submodule, m);
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}
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}
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log_assert(sort.sort());
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return sort.sorted;
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}
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struct AbcNewPass : public ScriptPass {
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AbcNewPass() : ScriptPass("abc_new", "(experimental) use ABC for SC technology mapping (new)")
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{
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@ -101,6 +120,15 @@ struct AbcNewPass : public ScriptPass {
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}
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if (check_label("prep_boxes")) {
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if (!help_mode) {
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for (auto mod : active_design->selected_whole_modules_warn()) {
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if (mod->get_bool_attribute(ID::abc9_box)) {
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mod->set_bool_attribute(ID::abc9_box, false);
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mod->set_bool_attribute(ID(abc9_deferred_box), true);
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}
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}
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}
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run("box_derive");
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run("abc9_ops -prep_box");
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}
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@ -109,7 +137,8 @@ struct AbcNewPass : public ScriptPass {
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std::vector<Module *> selected_modules;
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if (!help_mode) {
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selected_modules = active_design->selected_whole_modules_warn();
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selected_modules = order_modules(active_design,
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active_design->selected_whole_modules_warn());
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active_design->selection_stack.emplace_back(false);
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} else {
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selected_modules = {nullptr};
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@ -131,15 +160,36 @@ struct AbcNewPass : public ScriptPass {
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active_design->selection().select(mod);
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}
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std::string script_save;
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if (!help_mode && mod->has_attribute(ID(abc9_script))) {
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script_save = active_design->scratchpad_get_string("abc9.script");
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active_design->scratchpad_set_string("abc9.script",
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mod->get_string_attribute(ID(abc9_script)));
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}
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run(stringf(" abc9_ops -write_box %s/input.box", tmpdir.c_str()));
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run(stringf(" write_xaiger2 -mapping_prep -map2 %s/input.map2 %s/input.xaig", tmpdir.c_str(), tmpdir.c_str()));
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run(stringf(" abc9_exe %s -cwd %s -box %s/input.box", exe_options.c_str(), tmpdir.c_str(), tmpdir.c_str()));
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run(stringf(" read_xaiger2 -sc_mapping -module_name %s -map2 %s/input.map2 %s/output.aig",
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modname.c_str(), tmpdir.c_str(), tmpdir.c_str()));
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if (!help_mode && mod->has_attribute(ID(abc9_script))) {
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if (script_save.empty())
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active_design->scratchpad_unset("abc9.script");
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else
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active_design->scratchpad_set_string("abc9.script", script_save);
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}
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if (!help_mode) {
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active_design->selection().selected_modules.clear();
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log_pop();
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if (mod->get_bool_attribute(ID(abc9_deferred_box))) {
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mod->set_bool_attribute(ID(abc9_deferred_box), false);
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mod->set_bool_attribute(ID::abc9_box, true);
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Pass::call_on_module(active_design, mod, "portarcs -draw -write");
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run("abc9_ops -prep_box");
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}
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}
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}
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