mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 11:55:52 +00:00
Code Activity

Merge branch 'YosysHQ:main' into main

Browse source
This commit is contained in:
Akash Levy 2024-12-11 12:00:34 -08:00 • committed by GitHub
commit caaef5ac14
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
21 changed files with 432 additions and 137 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/verilog/verilog_backend.cc
View file

@ -1087,7 +1087,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == ID($_BUF_)) {
if (cell->type.in(ID($_BUF_), ID($buf))) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");