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Rename memory tests to lutram, add more xilinx tests

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This commit is contained in:
Eddie Hung 2019-12-12 17:44:37 -08:00
parent 9ab1feeaf1
commit caab66111e
9 changed files with 156 additions and 53 deletions
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6
tests/arch/ice40/memory.ys → tests/arch/ice40/lutram.ys
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@ -1,5 +1,5 @@
read_verilog ../common/memory.v
hierarchy -top top
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
@ -10,6 +10,6 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
cd lutram_1w1r
select -assert-count 1 t:SB_RAM40_4K
select -assert-none t:SB_RAM40_4K %% t:* %D