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Rename memory tests to lutram, add more xilinx tests

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This commit is contained in:
Eddie Hung 2019-12-12 17:44:37 -08:00
parent 9ab1feeaf1
commit caab66111e
9 changed files with 156 additions and 53 deletions
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tests/arch/gowin/lutram.ys Normal file
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read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
proc
memory -nomap
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#ERROR: Called with -verify and proof did fail!
#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 8 t:RAM16S4
# other logic present that is not simple
#select -assert-none t:RAM16S4 %% t:* %D