mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Added design->rename(module, new_name)

Browse source
This commit is contained in:
Clifford Wolf 2015-06-30 01:37:59 +02:00
parent df0163cd2b
commit caa274ada6
3 changed files with 9 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

7
kernel/rtlil.cc
View file

@ -444,6 +444,13 @@ void RTLIL::Design::remove(RTLIL::Module *module)
delete module;
}
void RTLIL::Design::rename(RTLIL::Module *module, RTLIL::IdString new_name)
{
modules_.erase(module->name);
module->name = new_name;
add(module);
}
void RTLIL::Design::sort()
{
scratchpad.sort();