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More idstring sort_by_* helpers and fixed tpl ordering in techmap

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This commit is contained in:
Clifford Wolf 2014-08-15 02:40:46 +02:00
parent 8ff71b5ae5
commit ca87116449
4 changed files with 22 additions and 10 deletions
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14
kernel/rtlil.h
View file

@ -255,12 +255,24 @@ namespace RTLIL
return log_id(str); return log_id(str);
} }
template <typename T> struct sort_by_name { template <typename T> struct sort_by_name_id {
bool operator()(T *a, T *b) const { bool operator()(T *a, T *b) const {
return a->name < b->name; return a->name < b->name;
} }
}; };
template <typename T> struct sort_by_name_str {
bool operator()(T *a, T *b) const {
return strcmp(a->name.c_str(), b->name.c_str()) < 0;
}
};
struct sort_by_id_str {
bool operator()(RTLIL::IdString a, RTLIL::IdString b) const {
return strcmp(a.c_str(), b.c_str()) < 0;
}
};
// see calc.cc for the implementation of this functions // see calc.cc for the implementation of this functions
RTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_not (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len); RTLIL::Const const_and (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);

8
passes/fsm/fsm_expand.cc
View file

@ -30,12 +30,12 @@ struct FsmExpand
RTLIL::Module *module; RTLIL::Module *module;
RTLIL::Cell *fsm_cell; RTLIL::Cell *fsm_cell;
SigMap assign_map; SigMap assign_map;
SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user; SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user;
CellTypes ct; CellTypes ct;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set; std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> merged_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set; std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> current_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set; std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> no_candidate_set;
bool already_optimized; bool already_optimized;
int limit_transitions; int limit_transitions;

4
passes/opt/opt_clean.cc
View file

@ -34,7 +34,7 @@ static int count_rm_cells, count_rm_wires;
static void rmunused_module_cells(RTLIL::Module *module, bool verbose) static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{ {
SigMap assign_map(module); SigMap assign_map(module);
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused; std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver; SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
@ -65,7 +65,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
while (queue.size() > 0) while (queue.size() > 0)
{ {
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue; std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
for (auto cell : queue) for (auto cell : queue)
unused.erase(cell); unused.erase(cell);
for (auto cell : queue) { for (auto cell : queue) {

6
passes/techmap/techmap.cc
View file

@ -251,7 +251,7 @@ struct TechmapWorker
} }
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells, bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool in_recursion) const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
{ {
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
@ -898,7 +898,7 @@ struct TechmapPass : public Pass {
} }
map->modules_.swap(modules_new); map->modules_.swap(modules_new);
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap; std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : map->modules_) { for (auto &it : map->modules_) {
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) { if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str()); char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
@ -960,7 +960,7 @@ struct FlattenPass : public Pass {
TechmapWorker worker; TechmapWorker worker;
worker.flatten_mode = true; worker.flatten_mode = true;
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap; std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : design->modules_) for (auto &it : design->modules_)
celltypeMap[it.first].insert(it.first); celltypeMap[it.first].insert(it.first);