mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-24 06:43:41 +00:00
More idstring sort_by_* helpers and fixed tpl ordering in techmap
This commit is contained in:
parent
8ff71b5ae5
commit
ca87116449
4 changed files with 22 additions and 10 deletions
|
@ -34,7 +34,7 @@ static int count_rm_cells, count_rm_wires;
|
|||
static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
|
||||
{
|
||||
SigMap assign_map(module);
|
||||
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
|
||||
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
|
||||
|
||||
SigSet<RTLIL::Cell*> wire2driver;
|
||||
for (auto &it : module->cells_) {
|
||||
|
@ -65,7 +65,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
|
|||
|
||||
while (queue.size() > 0)
|
||||
{
|
||||
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
|
||||
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
|
||||
for (auto cell : queue)
|
||||
unused.erase(cell);
|
||||
for (auto cell : queue) {
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue