From ca7d94af9953f372da0a3e77780f8b3c2f873440 Mon Sep 17 00:00:00 2001
From: Gary Wong <gtw@gnu.org>
Date: Sat, 31 May 2025 22:38:44 -0600
Subject: [PATCH] verilog: improve string literal matching speed (fixes #5076)

Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.
---
 frontends/verilog/verilog_lexer.l | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 8a3734302..8148748d8 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s
 }
 
 \"		{ BEGIN(STRING); }
-<STRING>\\.	{ yymore(); real_location = old_location; }
+<STRING>([^\"]|\\.)+	{ yymore(); real_location = old_location; }
 <STRING>\"	{
 	BEGIN(0);
 	char *yystr = strdup(yytext);
@@ -376,7 +376,6 @@ TIME_SCALE_SUFFIX [munpf]?s
 	free(yystr);
 	return TOK_STRING;
 }
-<STRING>.	{ yymore(); real_location = old_location; }
 
 and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
 	yylval->string = new std::string(yytext);