mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 04:28:18 +00:00
Code Activity

abc9.script.* constpad entries to start with '+'

Browse source
This commit is contained in:
Eddie Hung 2020-01-09 17:17:47 -08:00
parent ef3e84aac9
commit ca70f96503
1 changed files with 8 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
passes/techmap/abc9.cc
View file

@ -278,8 +278,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
} else } else
abc9_script += stringf("source %s", script_file.c_str()); abc9_script += stringf("source %s", script_file.c_str());
} else if (!lut_costs.empty() || !lut_file.empty()) { } else if (!lut_costs.empty() || !lut_file.empty()) {
abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast") abc9_script += fast_mode ? RTLIL::constpad.at("abc9.script.default.fast").substr(1,std::string::npos)
: RTLIL::constpad.at("abc9.script.default"); : RTLIL::constpad.at("abc9.script.default").substr(1,std::string::npos);
} else } else
log_abort(); log_abort();
@ -732,11 +732,11 @@ struct Abc9Pass : public Pass {
Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { } Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
void on_register() YS_OVERRIDE void on_register() YS_OVERRIDE
{ {
RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs"; RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs"; RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}"; RTLIL::constpad["abc9.script.default.fast"] = "+&if {C} {W} {D} {R}";
// Based on ABC's &flow // Based on ABC's &flow
RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \ RTLIL::constpad["abc9.script.flow"] = "+&scorr; &sweep;" \
/* Round 1 */ \ /* Round 1 */ \
"&unmap; &if {C} {W} {D} {R}; &mfs;" \ "&unmap; &if {C} {W} {D} {R}; &mfs;" \
"&st; &dsdb;" \ "&st; &dsdb;" \
@ -753,7 +753,7 @@ struct Abc9Pass : public Pass {
"&blut -a -K 6;" \ "&blut -a -K 6;" \
"&unmap; &if {C} {W} {D} {R} -v; &mfs"; "&unmap; &if {C} {W} {D} {R} -v; &mfs";
// Based on ABC's &flow2 // Based on ABC's &flow2
RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \ RTLIL::constpad["abc9.script.flow2"] = "+&scorr; &sweep;" \
/* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ /* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\ /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
"&load; &st; &sopb -R 10 -C 4; " \ "&load; &st; &sopb -R 10 -C 4; " \
@ -761,7 +761,7 @@ struct Abc9Pass : public Pass {
/* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\ /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
"&load"; "&load";
// Based on ABC's &flow3 // Based on ABC's &flow3
RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \ RTLIL::constpad["abc9.script.flow3"] = "+&scorr; &sweep;" \
"&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\ "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
"&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\ "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\ "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\