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Better preserve wires when flattening (in comparison to techmap)

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This commit is contained in:
Clifford Wolf 2014-02-17 09:44:39 +01:00
parent 37cbb1ca60
commit ca53ef5098
1 changed files with 12 additions and 12 deletions
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24
passes/techmap/techmap.cc
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@ -151,18 +151,18 @@ struct TechmapWorker
if (c.second.width < c.first.width)
c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
assert(c.first.width == c.second.width);
#if 0
// more conservative approach:
// connect internal and external wires
module->connections.push_back(c);
#else
// approach that yields nicer outputs:
// replace internal wires that are connected to external wires
if (w->port_output)
port_signal_map.add(c.second, c.first);
else
port_signal_map.add(c.first, c.second);
#endif
if (flatten_mode) {
// more conservative approach:
// connect internal and external wires
module->connections.push_back(c);
} else {
// approach that yields nicer outputs:
// replace internal wires that are connected to external wires
if (w->port_output)
port_signal_map.add(c.second, c.first);
else
port_signal_map.add(c.first, c.second);
}
}
for (auto &it : tpl->cells) {