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Fix ECP5 cells_sim for iverilog

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This commit is contained in:
Miodrag Milanovic 2019-03-01 19:25:23 +01:00
parent 60e3c38054
commit ca2b3feed8
1 changed files with 3 additions and 2 deletions
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5
techlibs/ecp5/cells_sim.v
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@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
wire srval;
generate generate
if (LSRMODE == "PRLD") if (LSRMODE == "PRLD")
wire srval = M; assign srval = M;
else else
localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0; assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
endgenerate endgenerate
initial Q = srval; initial Q = srval;