mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-20 11:22:05 +00:00
verilog: fix build dependency graph
This commit is contained in:
parent
e17ed5df88
commit
ca24169659
1 changed files with 1 additions and 0 deletions
|
@ -10,6 +10,7 @@ frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
|
|||
|
||||
frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
|
||||
|
||||
frontends/verilog/verilog_frontend.o: frontends/verilog/verilog_parser.tab.hh
|
||||
frontends/verilog/preproc.o: frontends/verilog/verilog_parser.tab.hh
|
||||
|
||||
frontends/verilog/verilog_lexer.h: frontends/verilog/verilog_parser.tab.hh
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue