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cellmatch: Rename -lut_attrs to -derive_luts; document option

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Martin Povišer 2024-10-16 11:43:54 +02:00
parent 8fb73e18ff
commit c9ed6d8dcf
2 changed files with 19 additions and 7 deletions
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18
passes/techmap/cellmatch.cc
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@ -155,18 +155,22 @@ struct CellmatchPass : Pass {
log("equivalent as long as their truth tables are identical upto a permutation of\n"); log("equivalent as long as their truth tables are identical upto a permutation of\n");
log("inputs and outputs. The supported number of inputs is limited to 6.\n"); log("inputs and outputs. The supported number of inputs is limited to 6.\n");
log("\n"); log("\n");
log(" cellmatch -derive_luts [module selection]\n");
log("\n");
log("For every port in each selected module, characterize its combinational\n");
log("function with a 'lut' attribute if possible.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *d) override void execute(std::vector<std::string> args, RTLIL::Design *d) override
{ {
log_header(d, "Executing CELLMATCH pass. (match cells)\n"); log_header(d, "Executing CELLMATCH pass. (match cells)\n");
size_t argidx; size_t argidx;
bool lut_attrs = false; bool derive_luts = false;
Design *lib = NULL; Design *lib = NULL;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-lut_attrs") { if (args[argidx] == "-derive_luts") {
// an undocumented debugging option derive_luts = true;
lut_attrs = true;
} else if (args[argidx] == "-lib" && argidx + 1 < args.size()) { } else if (args[argidx] == "-lib" && argidx + 1 < args.size()) {
if (!saved_designs.count(args[++argidx])) if (!saved_designs.count(args[++argidx]))
log_cmd_error("No design '%s' found!\n", args[argidx].c_str()); log_cmd_error("No design '%s' found!\n", args[argidx].c_str());
@ -177,8 +181,8 @@ struct CellmatchPass : Pass {
} }
extra_args(args, argidx, d); extra_args(args, argidx, d);
if (!lib && !lut_attrs) if (!lib && !derive_luts)
log_cmd_error("Missing required -lib option.\n"); log_cmd_error("Missing required -lib or -derive_luts option.\n");
struct Target { struct Target {
Module *module; Module *module;
@ -218,7 +222,7 @@ struct CellmatchPass : Pass {
SigSpec inputs = module_inputs(m); SigSpec inputs = module_inputs(m);
SigSpec outputs = module_outputs(m); SigSpec outputs = module_outputs(m);
if (lut_attrs) { if (derive_luts) {
int no = 0; int no = 0;
for (auto bit : outputs) { for (auto bit : outputs) {
log_assert(bit.is_wire()); log_assert(bit.is_wire());

8
tests/techmap/cellmatch.ys
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@ -77,3 +77,11 @@ opt_clean
equiv_induct equiv equiv_induct equiv
equiv_status -assert equiv_status -assert
design -reset
design -load gatelib
cellmatch -derive_luts
select -assert-any bufgate/w:Y a:lut=2'b10 %i
select -assert-any reducegate/w:X a:lut=8'b10000000 %i
select -assert-any reducegate/w:Y a:lut=8'b11111110 %i
select -assert-any fagate/w:X a:lut=8'b10010110 %i
select -assert-any fagate/w:Y a:lut=8'b11101000 %i