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If not multiclock, output only on clock edges

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This commit is contained in:
Miodrag Milanovic 2022-04-22 12:03:39 +02:00
parent 75032a565d
commit c989adcc2d
1 changed files with 18 additions and 0 deletions
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18
passes/sat/sim.cc
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@ -1782,6 +1782,12 @@ struct AIWWriter : public OutputWriter
log_error("Index %d for wire %s is out of range\n", index, log_signal(w));
if (type == "input") {
aiw_inputs[variable] = SigBit(w,index-w->start_offset);
if (worker->clock.count(escaped_s)) {
clocks[variable] = true;
}
if (worker->clockn.count(escaped_s)) {
clocks[variable] = false;
}
} else if (type == "init") {
aiw_inits[variable] = SigBit(w,index-w->start_offset);
} else if (type == "latch") {
@ -1823,6 +1829,17 @@ struct AIWWriter : public OutputWriter
first = false;
}
bool skip = false;
for (auto it : clocks)
{
auto val = it.second ? State::S1 : State::S0;
SigBit bit = aiw_inputs.at(it.first);
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
if (v == val)
skip = true;
}
if (skip)
continue;
for (int i = 0;; i++)
{
if (aiw_inputs.count(i)) {
@ -1852,6 +1869,7 @@ struct AIWWriter : public OutputWriter
std::ofstream aiwfile;
dict<int, std::pair<SigBit, bool>> aiw_latches;
dict<int, SigBit> aiw_inputs, aiw_inits;
dict<int, bool> clocks;
std::map<Wire*,int> mapping;
};