From c96e19bd436022d214cede1dcaf11910cfadbdf1 Mon Sep 17 00:00:00 2001
From: Lofty <dan.ravensloft@gmail.com>
Date: Tue, 10 May 2022 19:12:39 +0100
Subject: [PATCH] abc9: break conflict between boxes and outputs

---
 backends/aiger/xaiger.cc |  6 +++++-
 tests/various/bug3311.ys | 29 +++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 1 deletion(-)
 create mode 100644 tests/various/bug3311.ys

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index e223f185e..755f32ce1 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -432,8 +432,12 @@ struct XAigerWriter
 			//   that has been padded to its full width
 			if (bit == State::Sx)
 				continue;
+			// A bit might be simultaneously a box output
+			//   and a primary output. The latter wins.
+			if (input_bits.count(bit))
+				continue;
 			if (aig_map.count(bit))
-				log_error("Visited AIG node more than once; this could be a combinatorial loop that has not been broken\n");
+				log_error("While visiting box outputs, found a signal bit more than once; this could be a combinatorial loop that has not been broken\n");
 			aig_map[bit] = 2*aig_m;
 		}
 
diff --git a/tests/various/bug3311.ys b/tests/various/bug3311.ys
new file mode 100644
index 000000000..59f0f58a8
--- /dev/null
+++ b/tests/various/bug3311.ys
@@ -0,0 +1,29 @@
+read_rtlil <<EOT
+# Generated by Yosys 0.16+61 (git sha1 3730db4b9, clang 13.0.1 -fPIC -Os)
+autoidx 16887
+attribute \blackbox 1
+module \TRELLIS_IO
+  parameter \DIR
+  wire inout 1 \B
+  wire input 2 \I
+  wire output 3 \O
+  wire input 4 \T
+end
+attribute \top 1
+module \icesugarpro_top
+  wire width 8 inout 1 \P5_pmod_low
+  attribute \hdlname "vt spi 1796"
+  cell $_DFF_PP0_ $auto$ff.cc:262:slice$16873
+    connect \C 1'x
+    connect \D 1'x
+    connect \Q \P5_pmod_low [3]
+    connect \R 1'x
+  end
+  connect \P5_pmod_low [7:4] 4'x
+end
+EOT
+
+read_verilog -lib -specify +/ecp5/cells_sim.v
+techmap -map +/ecp5/cells_map.v
+abc9
+