From c952ab417f1ac0a5e21aa0ce49e552bb70c1c3fe Mon Sep 17 00:00:00 2001 From: George Rennie Date: Sat, 26 Apr 2025 12:03:50 +0200 Subject: [PATCH] opt_expr: only sign extend shift arguments for arithmetic right shift --- passes/opt/opt_expr.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index df969daf0..74f5b386a 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1315,13 +1315,14 @@ skip_fine_alu: RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int()); - // Limit indexing to the size of a, which is behaviourally identical (result is all 0) - // and avoids integer overflow of i + shift_bits when e.g. ID::B == INT_MAX - shift_bits = min(shift_bits, GetSize(sig_a)); - if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y)) sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + // Limit indexing to the size of a, which is behaviourally identical (result is all 0) + // and avoids integer overflow of i + shift_bits when e.g. ID::B == INT_MAX. + // We do this after sign-extending a so this accounts for the output size + shift_bits = min(shift_bits, GetSize(sig_a)); + for (int i = 0; i < GetSize(sig_y); i++) { int idx = i + shift_bits; if (0 <= idx && idx < GetSize(sig_a))