mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-19 17:50:26 +00:00
Code Activity

Remove GHDL and add mixed SV-VHDL support

Browse source
This commit is contained in:
Akash Levy 2024-10-20 23:29:33 -07:00
parent 10a352b8de
commit c94eac14b9
4 changed files with 13 additions and 933 deletions
Download patch file Download diff file Expand all files Collapse all files

6
Makefile
View file

@ -19,7 +19,6 @@ ENABLE_GHDL := 0
ENABLE_SLANG := 0
ENABLE_VERIFIC := 1
ENABLE_VERIFIC_SYSTEMVERILOG := 1
ENABLE_VERIFIC_GHDL := 0
ENABLE_VERIFIC_VHDL := 1
ENABLE_VERIFIC_HIER_TREE := 1
ENABLE_VERIFIC_SILIMATE_EXTENSIONS := 1
@ -524,9 +523,6 @@ ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
VERIFIC_COMPONENTS += verilog
endif
endif
ifeq ($(ENABLE_VERIFIC_GHDL),1)
CXXFLAGS += -DVERIFIC_GHDL_SUPPORT
endif
ifeq ($(ENABLE_VERIFIC_VHDL),1)
VERIFIC_COMPONENTS += vhdl
CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
@ -701,8 +697,6 @@ OBJS += libs/minisat/SimpSolver.o
OBJS += libs/minisat/Solver.o
OBJS += libs/minisat/System.o
OBJS += libs/whereami/whereami.o
ifeq ($(ENABLE_ZLIB),1)
OBJS += libs/fst/fstapi.o
OBJS += libs/fst/fastlz.o