mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 03:02:30 +00:00
sdc: simple mode, remove per-tool stubs
This commit is contained in:
Emil J. Tywoniak
parent
b5c40b6ed4
commit
c9488c4fd0
2 changed files with 160 additions and 261 deletions
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@ -5,6 +5,7 @@
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#include <tcl.h>
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#include <list>
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#include <regex>
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#include <optional>
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USING_YOSYS_NAMESPACE
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@ -12,6 +13,11 @@ PRIVATE_NAMESPACE_BEGIN
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struct SdcObjects {
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enum CollectMode {
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SimpleGetter,
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FullGetter,
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FullConstraint,
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} collect_mode;
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std::vector<std::string> design_ports;
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std::vector<std::pair<std::string, Cell*>> design_cells;
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std::vector<std::pair<std::string, Cell*>> design_pins;
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@ -86,26 +92,26 @@ struct SdcObjects {
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constrained_cells.sort();
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constrained_pins.sort();
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constrained_nets.sort();
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log("Design ports:\n");
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for (auto name : design_ports) {
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log("\t%s\n", name.c_str());
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}
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log("Design cells:\n");
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for (auto [name, cell] : design_cells) {
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(void)cell;
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log("\t%s\n", name.c_str());
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}
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log("Design pins:\n");
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for (auto [name, pin] : design_pins) {
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(void)pin;
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log("\t%s\n", name.c_str());
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}
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log("Design nets:\n");
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for (auto [name, net] : design_nets) {
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(void)net;
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log("\t%s\n", name.c_str());
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}
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log("\n");
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// log("Design ports:\n");
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// for (auto name : design_ports) {
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// log("\t%s\n", name.c_str());
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// }
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// log("Design cells:\n");
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// for (auto [name, cell] : design_cells) {
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// (void)cell;
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// log("\t%s\n", name.c_str());
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// }
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// log("Design pins:\n");
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// for (auto [name, pin] : design_pins) {
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// (void)pin;
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// log("\t%s\n", name.c_str());
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// }
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// log("Design nets:\n");
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// for (auto [name, net] : design_nets) {
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// (void)net;
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// log("\t%s\n", name.c_str());
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// }
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// log("\n");
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log("Constrained ports:\n");
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for (auto name : constrained_ports) {
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log("\t%s\n", name.c_str());
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@ -158,12 +164,13 @@ struct MatchConfig {
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};
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static bool matches(std::string name, const std::string& pat, const MatchConfig& config) {
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(void)config;
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// TODO implement full mode
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return name == pat;
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}
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static int sdc_get_pins_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
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{
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(void)interp;
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auto* objects = (SdcObjects*)data;
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// When this flag is present, the search for the pattern is made in all positions in the hierarchy.
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bool hierarchical_flag = false;
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@ -192,6 +199,14 @@ static int sdc_get_pins_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_O
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for (; i < objc; i++) {
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patterns.push_back(Tcl_GetString(objv[i]));
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}
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if (objects->collect_mode == SdcObjects::CollectMode::SimpleGetter) {
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if (regexp_flag || hierarchical_flag || nocase_flag || separator != "/" || of_objects) {
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log_error("get_pins got unexpected flags in simple mode\n");
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}
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if (patterns.size() != 1) {
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log_error("get_pins got unexpected number of patterns in simple mode\n");
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}
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}
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MatchConfig config(regexp_flag, nocase_flag, hierarchical_flag);
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std::vector<std::pair<std::string, Cell*>> resolved;
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@ -209,12 +224,9 @@ static int sdc_get_pins_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_O
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Tcl_Obj *result = Tcl_NewListObj(resolved.size(), nullptr);
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for (auto obj : resolved) {
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Tcl_ListObjAppendElement(interp, result, Tcl_NewStringObj(obj.first.c_str(), obj.first.size()));
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objects->constrained_pins.insert(obj);
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if (objects->collect_mode != SdcObjects::CollectMode::FullConstraint)
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objects->constrained_pins.insert(obj);
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}
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(void)hierarchical_flag;
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(void)regexp_flag;
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(void)nocase_flag;
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(void)of_objects;
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if (separator != "/") {
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Tcl_SetResult(interp, (char *)"Only '/' accepted as separator", TCL_STATIC);
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@ -227,7 +239,6 @@ static int sdc_get_pins_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_O
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static int sdc_get_ports_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
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{
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(void)interp;
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auto* objects = (SdcObjects*)data;
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bool regexp_flag = false;
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bool nocase_flag = false;
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@ -242,6 +253,14 @@ static int sdc_get_ports_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_
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for (; i < objc; i++) {
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patterns.push_back(Tcl_GetString(objv[i]));
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}
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if (objects->collect_mode == SdcObjects::CollectMode::SimpleGetter) {
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if (regexp_flag || nocase_flag) {
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log_error("get_ports got unexpected flags in simple mode\n");
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}
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if (patterns.size() != 1) {
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log_error("get_ports got unexpected number of patterns in simple mode\n");
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}
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}
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MatchConfig config(regexp_flag, nocase_flag, false);
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std::vector<std::string> resolved;
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for (auto pat : patterns) {
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@ -258,14 +277,89 @@ static int sdc_get_ports_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_
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Tcl_Obj *result = Tcl_NewListObj(resolved.size(), nullptr);
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for (auto obj : resolved) {
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Tcl_ListObjAppendElement(interp, result, Tcl_NewStringObj(obj.c_str(), obj.size()));
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objects->constrained_ports.insert(obj);
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if (objects->collect_mode != SdcObjects::CollectMode::FullConstraint)
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objects->constrained_ports.insert(obj);
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}
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(void)regexp_flag;
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(void)nocase_flag;
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Tcl_SetObjResult(interp, result);
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return TCL_OK;
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}
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std::optional<std::tuple<std::string, std::string>> split_at(std::string s)
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{
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size_t pos = s.find('@');
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if (pos == std::string::npos)
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return std::nullopt;
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return std::make_tuple(s.substr(0, pos), s.substr(pos + 1));
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}
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// Whether string or list of strings, apply op to each string
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void apply_args(Tcl_Interp *interp, std::function<void(const char*)> op, Tcl_Obj* obj)
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{
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int length;
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Tcl_Obj **value_list;
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if (Tcl_ListObjGetElements(interp, obj, &length, &value_list) == TCL_OK) {
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for (int i = 0; i < length; i++) {
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op(Tcl_GetString(value_list[i]));
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}
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} else {
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op(Tcl_GetString(obj));
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}
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}
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static int ys_track_typed_key_cmd(ClientData data, Tcl_Interp *interp, int objc, Tcl_Obj* const objv[])
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{
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log("ys_track_typed_key_cmd\n");
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auto* objects = (SdcObjects*)data;
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if (objc != 5)
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log_error("ys_track_typed_key: Unexpected number of arguments: %d (expected 5)\n", objc);
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if (objects->collect_mode != SdcObjects::CollectMode::FullConstraint)
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return TCL_OK;
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std::string key_name = Tcl_GetString(objv[1]);
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Tcl_Obj* key_value = objv[2];
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std::string key_expect_type = Tcl_GetString(objv[3]);
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std::string proc_name = Tcl_GetString(objv[4]);
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auto track_typed = [key_expect_type, objects, proc_name, key_name](const char* str) -> void {
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auto split = split_at(str);
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if (!split)
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log_error("%s: key %s should be a typed SDC object, but is something weird: %s\n",
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proc_name.c_str(), key_name.c_str(), str);
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if (key_expect_type == "pin") {
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log("PIN! %s\n", str);
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bool found = false;
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for (auto [name, pin] : objects->design_pins) {
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if (name + "/" + pin->name.str() == str) {
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found = true;
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objects->constrained_pins.insert(std::make_pair(name, pin));
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break; // resolved, expected unique
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}
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}
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if (!found)
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log_error("%s: pin %s not found\n", proc_name.c_str(), str);
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} else if (key_expect_type == "port") {
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bool found = false;
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for (auto name : objects->design_ports) {
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if (name == str) {
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found = true;
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objects->constrained_ports.insert(name);
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break; // resolved, expected unique
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}
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}
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if (!found)
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log_error("%s: port %s not found\n", proc_name.c_str(), str);
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} else {
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// TODO
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log_warning("%s: unsupported type %s\n", proc_name.c_str(), key_expect_type.c_str());
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}
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};
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apply_args(interp, track_typed, key_value);
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return TCL_OK;
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}
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class SDCInterpreter
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{
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@ -290,8 +384,10 @@ public:
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log_error("Tcl_Init() call failed - %s\n",Tcl_ErrnoMsg(Tcl_GetErrno()));
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objects = std::make_unique<SdcObjects>(design);
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objects->collect_mode = SdcObjects::CollectMode::FullConstraint;
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Tcl_CreateObjCommand(interp, "get_pins", sdc_get_pins_cmd, (ClientData) objects.get(), NULL);
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Tcl_CreateObjCommand(interp, "get_ports", sdc_get_ports_cmd, (ClientData) objects.get(), NULL);
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Tcl_CreateObjCommand(interp, "ys_track_typed_key", ys_track_typed_key_cmd, (ClientData) objects.get(), NULL);
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return interp;
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}
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};
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@ -301,17 +397,33 @@ struct SdcPass : public Pass {
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// TODO help
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SdcPass() : Pass("sdc", "sniff at some SDC") { }
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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if (args.size() < 2)
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log_cmd_error("Missing SDC file.\n");
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// if (args.size() < 2)
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// log_cmd_error("Missing SDC file.\n");
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// TODO optional extra stub file
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size_t argidx;
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std::vector<std::string> opensta_stubs_paths;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-stubs" && argidx+1 < args.size()) {
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opensta_stubs_paths.push_back(args[++argidx]);
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continue;
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}
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break;
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}
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if (argidx >= args.size())
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log_cmd_error("Missing SDC file.\n");
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std::string sdc_path = args[argidx];
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SDCInterpreter& sdc = SDCInterpreter::get();
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Tcl_Interp *interp = sdc.fresh_interp(design);
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Tcl_Preserve(interp);
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std::string stub_path = "+/sdc/stubs.sdc";
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rewrite_filename(stub_path);
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if (Tcl_EvalFile(interp, stub_path.c_str()) != TCL_OK)
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log_cmd_error("SDC interpreter returned an error in stub file: %s\n", Tcl_GetStringResult(interp));
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if (Tcl_EvalFile(interp, args[1].c_str()) != TCL_OK)
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log_cmd_error("SDC interpreter returned an error in stub preamble file: %s\n", Tcl_GetStringResult(interp));
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for (auto path : opensta_stubs_paths)
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if (Tcl_EvalFile(interp, path.c_str()) != TCL_OK)
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log_cmd_error("SDC interpreter returned an error in OpenSTA stub file %s: %s\n", path.c_str(), Tcl_GetStringResult(interp));
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if (Tcl_EvalFile(interp, sdc_path.c_str()) != TCL_OK)
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log_cmd_error("SDC interpreter returned an error: %s\n", Tcl_GetStringResult(interp));
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sdc.objects->dump();
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Tcl_Release(interp);
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@ -1,234 +1,21 @@
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# with Tcl's eager evaluation, we will still eval args if they're unused by a stub
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proc stub {function_name} {
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proc $function_name {args} {}
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proc $function_name {args} "puts \"stubbed $function_name\""
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}
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# OpenROAD
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proc get_name {thing} {
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return thing
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}
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proc get_full_name {thing} {
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return thing
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proc is_suppressed {args} {
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return 0
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}
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proc create_clock {args} {
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return "CLOCK@"
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}
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proc get_clocks {args} {
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return "CLOCK@"
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}
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# Vivado UG903
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stub add_cells_to_pblock
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stub add_to_power_rail
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stub all_clocks
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stub all_cpus
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stub all_dsps
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stub all_fanin
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stub all_fanout
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stub all_ffs
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stub all_hsios
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stub all_inputs
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stub all_latches
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stub all_outputs
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stub all_rams
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stub all_registers
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stub connect_debug_port
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stub create_clock
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stub create_debug_core
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stub create_debug_port
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stub create_generated_clock
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stub create_macro
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stub create_pblock
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stub create_power_rail
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stub create_property
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stub create_waiver
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stub current_design
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stub current_instance
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stub delete_macros
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stub delete_pblock
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stub delete_power_rails
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stub endgroup
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stub get_bel_pins
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stub get_bels
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stub get_clocks
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stub get_debug_cores
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stub get_debug_ports
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stub get_generated_clocks
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stub get_hierarchy_separator
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stub get_iobanks
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stub get_macros
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stub get_nodes
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stub get_package_pins
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stub get_path_groups
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stub get_pblocks
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stub get_pips
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stub get_pkgpin_bytegroups
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stub get_pkgpin_nibbles
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stub get_power_rails
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stub get_property
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stub get_site_pins
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stub get_site_pips
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stub get_sites
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stub get_slrs
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stub get_speed_models
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stub get_tiles
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stub get_timing_arcs
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stub group_path
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stub make_diff_pair_ports
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stub remove_cells_from_pblock
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stub remove_from_power_rail
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stub reset_operating_conditions
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stub reset_switching_activity
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stub resize_pblock
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stub set_bus_skew
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stub set_case_analysis
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stub set_clock_groups
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stub set_clock_latency
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stub set_clock_sense
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stub set_clock_uncertainty
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stub set_data_check
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stub set_disable_timing
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stub set_external_delay
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stub set_false_path
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stub set_hierarchy_separator
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stub set_input_delay
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stub set_input_jitter
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stub set_load
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stub set_logic_dc
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stub set_logic_one
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stub set_logic_unconnected
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stub set_logic_zero
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stub set_max_delay
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stub set_max_time_borrow
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stub set_min_delay
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stub set_multicycle_path
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stub set_operating_conditions
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stub set_output_delay
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stub set_package_pin_val
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stub set_power_opt
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stub set_propagated_clock
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stub set_property
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stub set_switching_activity
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stub set_system_jitter
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stub set_units
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stub startgroup
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stub update_macro
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# OpenSTA
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stub source_
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stub write_sdc
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stub current_instance
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stub set_hierarchy_separator
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stub check_path_divider
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stub set_units
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stub check_unit
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stub unit_prefix_scale
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stub check_unit_scale
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stub all_clocks
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stub all_inputs
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stub all_outputs
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stub all_registers
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stub current_design
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stub filter_objs
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stub check_nocase_flag
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stub find_liberty_libraries_matching
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stub create_clock
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stub delete_clock
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stub create_generated_clock
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stub delete_generated_clock
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stub remove_gclk_cmd
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stub group_path
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stub check_exception_pins
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stub set_clock_gating_check
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stub set_clock_gating_check1
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stub set_clock_groups
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stub unset_clock_groups
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stub unset_clk_groups_cmd
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stub set_clock_latency
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stub unset_clock_latency
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stub unset_clk_latency_cmd
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stub set_sense
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stub set_clock_sense
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stub set_clock_sense_cmd1
|
||||
stub set_clock_transition
|
||||
stub unset_clock_transition
|
||||
stub set_clock_uncertainty
|
||||
stub unset_clock_uncertainty
|
||||
stub unset_clk_uncertainty_cmd
|
||||
stub set_data_check
|
||||
stub unset_data_check
|
||||
stub unset_data_checks_cmd
|
||||
stub set_disable_timing
|
||||
stub set_disable_timing_instance
|
||||
stub parse_disable_inst_ports
|
||||
stub port_members
|
||||
stub set_disable_timing_cell
|
||||
stub parse_disable_cell_ports
|
||||
stub unset_disable_timing
|
||||
stub unset_disable_cmd
|
||||
stub unset_disable_timing_cell
|
||||
stub unset_disable_timing_instance
|
||||
stub set_false_path
|
||||
stub set_ideal_latency
|
||||
stub set_ideal_network
|
||||
stub set_ideal_transition
|
||||
stub set_input_delay
|
||||
stub set_port_delay
|
||||
stub unset_input_delay
|
||||
stub set_max_delay
|
||||
stub set_path_delay
|
||||
stub set_max_time_borrow
|
||||
stub set_min_delay
|
||||
stub set_min_pulse_width
|
||||
stub set_multicycle_path
|
||||
stub unset_path_exceptions
|
||||
stub unset_path_exceptions_cmd
|
||||
stub set_output_delay
|
||||
stub unset_output_delay
|
||||
stub unset_port_delay
|
||||
stub set_propagated_clock
|
||||
stub unset_propagated_clock
|
||||
stub set_case_analysis
|
||||
stub unset_case_analysis
|
||||
stub set_drive
|
||||
stub set_driving_cell
|
||||
stub port_direction_any_output
|
||||
stub set_fanout_load
|
||||
stub set_input_transition
|
||||
stub set_load
|
||||
stub set_logic_dc
|
||||
stub set_logic_value
|
||||
stub set_logic_one
|
||||
stub set_logic_zero
|
||||
stub set_max_area
|
||||
stub set_max_capacitance
|
||||
stub set_capacitance_limit
|
||||
stub set_max_fanout
|
||||
stub set_fanout_limit
|
||||
stub set_max_transition
|
||||
stub set_port_fanout_number
|
||||
stub set_resistance
|
||||
stub set_timing_derate
|
||||
stub unset_timing_derate
|
||||
stub parse_from_arg
|
||||
stub parse_thrus_arg
|
||||
stub parse_to_arg
|
||||
stub parse_to_arg1
|
||||
stub delete_from_thrus_to
|
||||
stub parse_comment_key
|
||||
stub set_min_capacitance
|
||||
stub set_operating_conditions
|
||||
stub parse_op_cond
|
||||
stub parse_op_cond_analysis_type
|
||||
stub set_wire_load_min_block_size
|
||||
stub set_wire_load_mode
|
||||
stub set_wire_load_model
|
||||
stub set_wire_load_selection_group
|
||||
stub set_voltage
|
||||
stub create_voltage_area
|
||||
stub set_level_shifter_strategy
|
||||
stub set_level_shifter_threshold
|
||||
stub set_max_dynamic_power
|
||||
stub set_max_leakage_power
|
||||
stub define_corners
|
||||
stub set_pvt
|
||||
stub set_pvt_min_max
|
||||
stub default_operating_conditions
|
||||
stub cell_regexp
|
||||
stub cell_regexp_hsc
|
||||
stub port_regexp
|
||||
stub port_regexp_hsc
|
||||
#stub ys_track_typed_key
|
||||
stub ys_track_untyped_key
|
||||
stub ys_err_key
|
||||
stub ys_err_flag
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue