diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 42c17aa9b..35fdb1976 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -32,16 +32,17 @@ USING_YOSYS_NAMESPACE using namespace RTLIL_BACKEND; YOSYS_NAMESPACE_BEGIN -void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design, DumpMode mode) { if (design && design->obj_src_id(obj) != Twine::Null) { TwineRef id = design->obj_src_id(obj); f << stringf("%s" "attribute \\src ", indent); - if (stringify) { + if (mode == DumpMode::Readable) { dump_const(f, RTLIL::Const(design->twines.str(id))); } else { dump_const(f, RTLIL::Const(stringf("@%zu", id))); - f << stringf(" # %s", design->twines.str(id).c_str()); + if (mode == DumpMode::Replayable) + f << stringf(" # %s", design->twines.str(id).c_str()); } f << stringf("\n"); } @@ -148,27 +149,27 @@ static std::string twine_handle(TwineRef ref) return stringf("%s@%zu", twine_is_public(ref) ? "$pub" : "$priv", (size_t)twine_untag(ref)); } -static std::string twine_ref(const RTLIL::Design *design, TwineRef ref, bool stringify) +static std::string twine_ref(const RTLIL::Design *design, TwineRef ref, DumpMode mode) { - if (stringify || twine_untag(ref) < STATIC_TWINE_END) + if (mode == DumpMode::Readable || twine_untag(ref) < STATIC_TWINE_END) return design->twines.str(ref); return twine_handle(ref); } -static std::string twine_cmt(const RTLIL::Design *design, TwineRef ref, bool stringify) +static std::string twine_cmt(const RTLIL::Design *design, TwineRef ref, DumpMode mode) { - if (stringify || twine_untag(ref) < STATIC_TWINE_END) + if (mode != DumpMode::Replayable || twine_untag(ref) < STATIC_TWINE_END) return ""; return stringf(" # %s", design->twines.str(ref).c_str()); } -void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint, bool stringify) +void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint, DumpMode mode) { if (chunk.wire == NULL) { dump_const(f, chunk.data, chunk.width, chunk.offset, autoint); } else { TwineRef wref = chunk.wire->name.ref(); - std::string name = (stringify || twine_untag(wref) < STATIC_TWINE_END) + std::string name = (mode == DumpMode::Readable || twine_untag(wref) < STATIC_TWINE_END) ? chunk.wire->name.str() : twine_handle(wref); if (chunk.width == chunk.wire->width && chunk.offset == 0) f << name; @@ -179,24 +180,24 @@ void RTLIL_BACKEND::dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, } } -void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint, bool stringify) +void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint, DumpMode mode) { if (sig.is_chunk()) { - dump_sigchunk(f, sig.as_chunk(), autoint, stringify); + dump_sigchunk(f, sig.as_chunk(), autoint, mode); } else { f << stringf("{ "); auto chunks = sig.chunks(); for (const auto& chunk : reversed(chunks)) { - dump_sigchunk(f, chunk, false, stringify); + dump_sigchunk(f, chunk, false, mode); f << stringf(" "); } f << stringf("}"); } } -void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, DumpMode mode) { - dump_attributes(f, indent, wire, design, stringify); + dump_attributes(f, indent, wire, design, mode); if (wire->driverCell_) { f << stringf("%s" "# driver %s %s\n", indent, wire->driverCell()->name, design->twines.str(wire->driverPort()).c_str()); @@ -216,12 +217,12 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL:: f << stringf("inout %d ", wire->port_id); if (wire->is_signed) f << stringf("signed "); - f << twine_ref(design, wire->name.ref(), stringify) << twine_cmt(design, wire->name.ref(), stringify) << "\n"; + f << twine_ref(design, wire->name.ref(), mode) << twine_cmt(design, wire->name.ref(), mode) << "\n"; } -void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design, DumpMode mode) { - dump_attributes(f, indent, memory, design, stringify); + dump_attributes(f, indent, memory, design, mode); f << stringf("%s" "memory ", indent); if (memory->width != 1) f << stringf("width %d ", memory->width); @@ -229,15 +230,15 @@ void RTLIL_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL f << stringf("size %d ", memory->size); if (memory->start_offset != 0) f << stringf("offset %d ", memory->start_offset); - f << twine_ref(design, memory->meta_->name, stringify) << twine_cmt(design, memory->meta_->name, stringify) << "\n"; + f << twine_ref(design, memory->meta_->name, mode) << twine_cmt(design, memory->meta_->name, mode) << "\n"; } -void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design, DumpMode mode) { - dump_attributes(f, indent, cell, design, stringify); + dump_attributes(f, indent, cell, design, mode); f << stringf("%s" "cell ", indent); - f << twine_ref(design, cell->type.ref(), stringify) << " " << twine_ref(design, cell->name.ref(), stringify) - << twine_cmt(design, cell->type.ref(), stringify) << twine_cmt(design, cell->name.ref(), stringify) << "\n"; + f << twine_ref(design, cell->type.ref(), mode) << " " << twine_ref(design, cell->name.ref(), mode) + << twine_cmt(design, cell->type.ref(), mode) << twine_cmt(design, cell->name.ref(), mode) << "\n"; for (const auto& [name, param] : reversed(cell->parameters)) { f << stringf("%s parameter%s%s%s %s ", indent, (param.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", @@ -249,53 +250,53 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: } for (const auto& [port, sig] : reversed(cell->connections_)) { f << stringf("%s connect ", indent); - f << twine_ref(design, port, stringify) << " "; - dump_sigspec(f, sig, true, stringify); - f << twine_cmt(design, port, stringify) << "\n"; + f << twine_ref(design, port, mode) << " "; + dump_sigspec(f, sig, true, mode); + f << twine_cmt(design, port, mode) << "\n"; } f << stringf("%s" "end\n", indent); } -void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design, DumpMode mode) { for (const auto& [lhs, rhs] : cs->actions) { f << stringf("%s" "assign ", indent); - dump_sigspec(f, lhs, true, stringify); + dump_sigspec(f, lhs, true, mode); f << stringf(" "); - dump_sigspec(f, rhs, true, stringify); + dump_sigspec(f, rhs, true, mode); f << stringf("\n"); } for (const auto& sw : cs->switches) - dump_proc_switch(f, indent, sw, design, stringify); + dump_proc_switch(f, indent, sw, design, mode); } -void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design, DumpMode mode) { - dump_attributes(f, indent, sw, design, stringify); + dump_attributes(f, indent, sw, design, mode); f << stringf("%s" "switch ", indent); - dump_sigspec(f, sw->signal, true, stringify); + dump_sigspec(f, sw->signal, true, mode); f << stringf("\n"); for (const auto case_ : sw->cases) { - dump_attributes(f, indent, case_, design, stringify); + dump_attributes(f, indent, case_, design, mode); f << stringf("%s case ", indent); for (size_t i = 0; i < case_->compare.size(); i++) { if (i > 0) f << stringf(" , "); - dump_sigspec(f, case_->compare[i], true, stringify); + dump_sigspec(f, case_->compare[i], true, mode); } f << stringf("\n"); - dump_proc_case_body(f, indent + " ", case_, design, stringify); + dump_proc_case_body(f, indent + " ", case_, design, mode); } f << stringf("%s" "end\n", indent); } -void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design, DumpMode mode) { f << stringf("%s" "sync ", indent); switch (sy->type) { @@ -304,7 +305,7 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT if (0) case RTLIL::STp: f << stringf("posedge "); if (0) case RTLIL::STn: f << stringf("negedge "); if (0) case RTLIL::STe: f << stringf("edge "); - dump_sigspec(f, sy->signal, true, stringify); + dump_sigspec(f, sy->signal, true, mode); f << stringf("\n"); break; case RTLIL::STa: f << stringf("always\n"); break; @@ -314,57 +315,57 @@ void RTLIL_BACKEND::dump_proc_sync(std::ostream &f, std::string indent, const RT for (const auto& [lhs, rhs] : sy->actions) { f << stringf("%s update ", indent); - dump_sigspec(f, lhs, true, stringify); + dump_sigspec(f, lhs, true, mode); f << stringf(" "); - dump_sigspec(f, rhs, true, stringify); + dump_sigspec(f, rhs, true, mode); f << stringf("\n"); } for (auto &it: sy->mem_write_actions) { - dump_attributes(f, indent, &it, design, stringify); + dump_attributes(f, indent, &it, design, mode); f << stringf("%s memwr %s ", indent, it.memid); - dump_sigspec(f, it.address, true, stringify); + dump_sigspec(f, it.address, true, mode); f << stringf(" "); - dump_sigspec(f, it.data, true, stringify); + dump_sigspec(f, it.data, true, mode); f << stringf(" "); - dump_sigspec(f, it.enable, true, stringify); + dump_sigspec(f, it.enable, true, mode); f << stringf(" "); dump_const(f, it.priority_mask); f << stringf("\n"); } } -void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design, bool stringify) +void RTLIL_BACKEND::dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design, DumpMode mode) { - dump_attributes(f, indent, proc, design, stringify); + dump_attributes(f, indent, proc, design, mode); f << stringf("%s" "process ", indent); - f << twine_ref(design, proc->meta_->name, stringify) << twine_cmt(design, proc->meta_->name, stringify) << "\n"; - dump_proc_case_body(f, indent + " ", &proc->root_case, design, stringify); + f << twine_ref(design, proc->meta_->name, mode) << twine_cmt(design, proc->meta_->name, mode) << "\n"; + dump_proc_case_body(f, indent + " ", &proc->root_case, design, mode); for (auto* sync : proc->syncs) - dump_proc_sync(f, indent + " ", sync, design, stringify); + dump_proc_sync(f, indent + " ", sync, design, mode); f << stringf("%s" "end\n", indent); } -void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right, bool stringify) +void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right, DumpMode mode) { f << stringf("%s" "connect ", indent); - dump_sigspec(f, left, true, stringify); + dump_sigspec(f, left, true, mode); f << stringf(" "); - dump_sigspec(f, right, true, stringify); + dump_sigspec(f, right, true, mode); f << stringf("\n"); } -void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool stringify) +void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, DumpMode mode) { bool print_header = flag_m || module->is_selected_whole(); bool print_body = !flag_n || !module->is_selected_whole(); if (print_header) { - dump_attributes(f, indent, module, design, stringify); + dump_attributes(f, indent, module, design, mode); f << stringf("%s" "module ", indent); - f << twine_ref(design, module->meta_->name, stringify) << twine_cmt(design, module->meta_->name, stringify) << "\n"; + f << twine_ref(design, module->meta_->name, mode) << twine_cmt(design, module->meta_->name, mode) << "\n"; if (!module->avail_parameters.empty()) { if (only_selected) @@ -388,28 +389,28 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (!only_selected || design->selected(module, wire)) { if (only_selected) f << stringf("\n"); - dump_wire(f, indent + " ", wire, design, stringify); + dump_wire(f, indent + " ", wire, design, mode); } for (const auto& [_, mem] : reversed(module->memories)) if (!only_selected || design->selected(module, mem)) { if (only_selected) f << stringf("\n"); - dump_memory(f, indent + " ", mem, design, stringify); + dump_memory(f, indent + " ", mem, design, mode); } for (const auto& [_, cell] : reversed(module->cells_)) if (!only_selected || design->selected(module, cell)) { if (only_selected) f << stringf("\n"); - dump_cell(f, indent + " ", cell, design, stringify); + dump_cell(f, indent + " ", cell, design, mode); } for (const auto& [_, process] : reversed(module->processes)) if (!only_selected || design->selected(module, process)) { if (only_selected) f << stringf("\n"); - dump_proc(f, indent + " ", process, design, stringify); + dump_proc(f, indent + " ", process, design, mode); } bool first_conn_line = true; @@ -427,7 +428,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu if (show_conn) { if (only_selected && first_conn_line) f << stringf("\n"); - dump_conn(f, indent + " ", lhs, rhs, stringify); + dump_conn(f, indent + " ", lhs, rhs, mode); first_conn_line = false; } } @@ -437,7 +438,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu f << stringf("%s" "end\n", indent); } -void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool stringify) +void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, DumpMode mode) { int init_autoidx = autoidx; @@ -457,7 +458,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (only_selected) f << stringf("\n"); f << stringf("autoidx %d\n", autoidx); - if (!stringify) + if (mode != DumpMode::Readable) dump_twines(f, design); } @@ -465,7 +466,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl if (!only_selected || design->selected_module(module->meta_->name)) { if (only_selected) f << stringf("\n"); - dump_module(f, "", module, design, only_selected, flag_m, flag_n, stringify); + dump_module(f, "", module, design, only_selected, flag_m, flag_n, mode); } } @@ -493,15 +494,22 @@ struct RTLILBackend : public Backend { log(" sort design in-place (used to be default).\n"); log("\n"); log(" -readable\n"); - log(" lose information for more readable files.\n"); - log(" Breaks perfect replayability.\n"); + log(" print human-readable names. Loses twine id information,\n"); + log(" breaking perfect replayability.\n"); + log("\n"); + log(" -small\n"); + log(" like the default replayable form but omit the `# name`\n"); + log(" comments, for smaller files.\n"); + log("\n"); + log("Without -readable or -small the output is fully replayable: twine\n"); + log("handles plus a `twines` pool section and `# name` comments.\n"); log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool selected = false; bool do_sort = false; - bool stringify = false; + DumpMode mode = DumpMode::Replayable; log_header(design, "Executing RTLIL backend.\n"); @@ -516,12 +524,12 @@ struct RTLILBackend : public Backend { do_sort = true; continue; } - if (arg == "-readable") { - stringify = true; + if (arg == "-readable" || arg == "-resolve-src") { + mode = DumpMode::Readable; continue; } - if (arg == "-resolve-src") { - stringify = true; + if (arg == "-small") { + mode = DumpMode::Small; continue; } break; @@ -534,7 +542,7 @@ struct RTLILBackend : public Backend { design->sort(); *f << stringf("# Generated by %s\n", yosys_maybe_version()); - RTLIL_BACKEND::dump_design(*f, design, selected, true, false, stringify); + RTLIL_BACKEND::dump_design(*f, design, selected, true, false, mode); } } RTLILBackend; @@ -563,14 +571,23 @@ struct DumpPass : public Pass { log(" like -outfile but append instead of overwrite\n"); log("\n"); log(" -readable\n"); - log(" lose information for more readable files.\n"); - log(" Breaks perfect replayability.\n"); + log(" print human-readable names. Loses twine id information,\n"); + log(" breaking perfect replayability.\n"); + log("\n"); + log(" -small\n"); + log(" like the default replayable form but omit the `# name`\n"); + log(" comments, for smaller output.\n"); + log("\n"); + log("Without -readable or -small the output is fully replayable (the same\n"); + log("form write_rtlil produces): twine handles plus a `twines` pool section\n"); + log("and `# name` comments.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { std::string filename; - bool flag_m = false, flag_n = false, append = false, stringify = false; + bool flag_m = false, flag_n = false, append = false; + DumpMode mode = DumpMode::Replayable; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -594,12 +611,12 @@ struct DumpPass : public Pass { flag_n = true; continue; } - if (arg == "-readable") { - stringify = true; + if (arg == "-readable" || arg == "-resolve-src") { + mode = DumpMode::Readable; continue; } - if (arg == "-resolve-src") { - stringify = true; + if (arg == "-small") { + mode = DumpMode::Small; continue; } break; @@ -623,7 +640,7 @@ struct DumpPass : public Pass { f = &buf; } - RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, stringify); + RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, mode); if (!empty) { delete f; diff --git a/backends/rtlil/rtlil_backend.h b/backends/rtlil/rtlil_backend.h index 3c38e3748..1f826bcfd 100644 --- a/backends/rtlil/rtlil_backend.h +++ b/backends/rtlil/rtlil_backend.h @@ -31,22 +31,30 @@ YOSYS_NAMESPACE_BEGIN namespace RTLIL_BACKEND { - void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design = nullptr, bool stringify = false); + // How names are rendered in the RTLIL text representation: + // Replayable - twine handles ($pub@N) + a `twines` pool section + + // `# name` comments. The default; perfectly replayable. + // Readable - real escaped names inline, no pool section, no comments. + // Matches the historic RTLIL look. Lossy: breaks replay. + // Small - like Replayable but omits the `# name` comments. + enum class DumpMode { Replayable, Readable, Small }; + + void dump_attributes(std::ostream &f, std::string indent, const RTLIL::AttrObject *obj, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); void dump_twines(std::ostream &f, const RTLIL::Design *design); void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true); - void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true, bool stringify = true); - void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true, bool stringify = true); - void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design = nullptr, bool stringify = false); - void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design = nullptr, bool stringify = false); - void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design = nullptr, bool stringify = false); - void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design = nullptr, bool stringify = false); - void dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design = nullptr, bool stringify = false); - void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design = nullptr, bool stringify = false); - void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design = nullptr, bool stringify = false); - void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right, bool stringify = true); - void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool stringify = false); - void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool stringify = false); + void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true, DumpMode mode = DumpMode::Replayable); + void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true, DumpMode mode = DumpMode::Replayable); + void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); + void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); + void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); + void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); + void dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); + void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); + void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc, const RTLIL::Design *design = nullptr, DumpMode mode = DumpMode::Replayable); + void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right, DumpMode mode = DumpMode::Replayable); + void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, DumpMode mode = DumpMode::Replayable); + void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, DumpMode mode = DumpMode::Replayable); } YOSYS_NAMESPACE_END