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Added support for inferring counters with reset to full scale instead of zero
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@ -95,6 +95,7 @@ struct CounterExtraction
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bool has_ce; //true if we have a clock enable
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bool has_ce; //true if we have a clock enable
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RTLIL::SigSpec rst; //reset pin
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RTLIL::SigSpec rst; //reset pin
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bool rst_inverted; //true if reset is active low
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bool rst_inverted; //true if reset is active low
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bool rst_to_max; //true if we reset to max instead of 0
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int count_value; //value we count from
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int count_value; //value we count from
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RTLIL::SigSpec ce; //clock signal
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RTLIL::SigSpec ce; //clock signal
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RTLIL::SigSpec clk; //clock enable, if any
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RTLIL::SigSpec clk; //clock enable, if any
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@ -237,10 +238,16 @@ int counter_tryextract(
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{
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{
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extract.has_reset = true;
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extract.has_reset = true;
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//Verify ARST_VALUE is zero.
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//Check polarity of reset - we may have to add an inverter later on!
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//Detect polarity inversions on reset.
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extract.rst_inverted = (count_reg->getParam("\\ARST_POLARITY").as_int() != 1);
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extract.rst_inverted = (count_reg->getParam("\\ARST_POLARITY").as_int() != 1);
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if(count_reg->getParam("\\ARST_VALUE").as_int() != 0)
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//Verify ARST_VALUE is zero or full scale
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int rst_value = count_reg->getParam("\\ARST_VALUE").as_int();
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if(rst_value == 0)
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extract.rst_to_max = false;
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else if(rst_value == extract.count_value)
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extract.rst_to_max = true;
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else
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return 23;
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return 23;
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//Save the reset
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//Save the reset
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@ -419,7 +426,7 @@ void counter_worker(
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"No init value found", //20
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"No init value found", //20
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"Underflow value is not equal to init value", //21
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"Underflow value is not equal to init value", //21
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"RESERVED, not implemented", //22, kept for compatibility but not used anymore
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"RESERVED, not implemented", //22, kept for compatibility but not used anymore
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"Reset is not to zero", //23
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"Reset is not to zero or COUNT_TO", //23
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"Clock enable configuration is unsupported" //24
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"Clock enable configuration is unsupported" //24
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};
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};
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