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Add fanoutbuf pass
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Akash Levy
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3 changed files with 600 additions and 0 deletions
402
tests/silimate/fanoutbuf.ys
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402
tests/silimate/fanoutbuf.ys
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# Test 1
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log -header "Simple input to output buffer > limit 4"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 2
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log -header "Simple input to output buffer = limit 4, should do nothing"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-none t:$buf
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design -reset
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log -pop
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# Test 3
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log -header "Simple input to output buffer = limit 4*4 + 1 = 17, should do two layers"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire w6,
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output wire w7,
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output wire w8,
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output wire w9,
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output wire w10,
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output wire w11,
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output wire w12,
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output wire w13,
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output wire w14,
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output wire w15,
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output wire w16,
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output wire w17
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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assign w6 = a;
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assign w7 = a;
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assign w8 = a;
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assign w9 = a;
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assign w10 = a;
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assign w11 = a;
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assign w12 = a;
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assign w13 = a;
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assign w14 = a;
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assign w15 = a;
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assign w16 = a;
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assign w17 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 5 t:$buf
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design -reset
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log -pop
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# Test 4
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log -header "Multi-bit signal fanout buffering"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire [3:0] w1,
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output wire [3:0] w2,
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output wire [3:0] w3,
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output wire [3:0] w4,
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output wire [3:0] w5
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should have 4 buffers (one per bit)
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 4 t:$buf
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design -reset
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log -pop
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# Test 5
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log -header "Custom fanout limit (limit 3)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf with limit 3 - should insert 1 buffer
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equiv_opt -assert fanoutbuf -limit 3
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 6
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log -header "Mixed fanout counts on different signals"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire x1,
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output wire x2
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);
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assign w1 = a; // a has fanout 5 (> limit 4)
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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assign x1 = b; // b has fanout 2 (< limit 4)
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assign x2 = b;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert 1 buffer for signal a only
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 7
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log -header "Logic gates with high fanout"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire w6
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);
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wire and_out;
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assign and_out = a & b;
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assign w1 = and_out;
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assign w2 = and_out;
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assign w3 = and_out;
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assign w4 = and_out;
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assign w5 = and_out;
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assign w6 = and_out;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert buffers for and_out
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 8
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log -header "Edge case: exactly limit+1 fanout"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5
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);
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assign w1 = a;
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assign w2 = a;
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assign w3 = a;
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assign w4 = a;
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assign w5 = a;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert exactly 1 buffer
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 9
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log -header "Complex expressions with intermediate signals"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5,
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output wire x1,
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output wire x2,
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output wire x3,
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output wire x4,
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output wire x5
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);
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wire intermediate1, intermediate2;
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assign intermediate1 = a & b;
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assign intermediate2 = intermediate1 | c;
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assign w1 = intermediate1;
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assign w2 = intermediate1;
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assign w3 = intermediate1;
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assign w4 = intermediate1;
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assign w5 = intermediate1;
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assign x1 = intermediate2;
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assign x2 = intermediate2;
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assign x3 = intermediate2;
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assign x4 = intermediate2;
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assign x5 = intermediate2;
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert buffers for both intermediates
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 2 t:$buf
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design -reset
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log -pop
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# Test 10
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log -header "Hierarchical design with fanout buffering"
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log -push
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design -reset
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read_verilog <<EOF
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module sub (
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input wire in,
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output wire out1,
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output wire out2,
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output wire out3,
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output wire out4,
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output wire out5
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);
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assign out1 = in;
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assign out2 = in;
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assign out3 = in;
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assign out4 = in;
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assign out5 = in;
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endmodule
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module top (
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input wire a,
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output wire w1,
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output wire w2,
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output wire w3,
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output wire w4,
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output wire w5
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);
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sub u1 (.in(a), .out1(w1), .out2(w2), .out3(w3), .out4(w4), .out5(w5));
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert buffers in sub module
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-count 1 t:$buf
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design -reset
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log -pop
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# Test 11
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log -header "Very high fanout requiring multiple buffer layers"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire [31:0] w
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);
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assign w = {32{a}}; // 32-bit fanout from single input
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endmodule
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EOF
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check -assert
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# Check equivalence after fanoutbuf - should insert multiple layers of buffers
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equiv_opt -assert fanoutbuf
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design -load postopt
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select -assert-min 8 t:$buf
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design -reset
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log -pop
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