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Revert back to using Verific naming

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This commit is contained in:
Akash Levy 2025-02-13 19:40:33 -08:00
parent aa515e8847
commit c8c97ea00b
10 changed files with 75 additions and 123 deletions
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4
tests/verific/rom_case.ys.DISABLED
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@ -1,4 +1,4 @@
import -sv <<EOF
verific -sv <<EOF
module rom(input clk, input [2:0] addr, (* ram_style = "block" *) output reg [7:0] data);
always @(posedge clk) begin
@ -30,7 +30,7 @@ select -assert-count 1 t:RAM_BLOCK_SDP
design -reset
import -vhdl <<EOF
verific -vhdl <<EOF
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;