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Revert back to using Verific naming

This commit is contained in:
Akash Levy 2025-02-13 19:40:33 -08:00
parent aa515e8847
commit c8c97ea00b
10 changed files with 75 additions and 123 deletions

View file

@ -1,4 +1,4 @@
import -formal <<EOF
verific -formal <<EOF
module top(clk);
input wire clk;