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Revert back to using Verific naming

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This commit is contained in:
Akash Levy 2025-02-13 19:40:33 -08:00
parent aa515e8847
commit c8c97ea00b
10 changed files with 75 additions and 123 deletions
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6
tests/verific/blackbox_ql.ys.DISABLED
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@ -1,6 +1,6 @@
import -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
import -sv <<EOF
verific -sv <<EOF
module top (
input wire [19:0] a,
input wire [17:0] b,
@ -35,7 +35,7 @@ endmodule
EOF
import -import top
verific -import top
hierarchy -top top
synth_quicklogic -family qlf_k6n10f
select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324