Revert back to using Verific naming

tests/verific/blackbox.ys.DISABLED

@@ -1,4 +1,4 @@
-import -sv -lib <<EOF
+verific -sv -lib <<EOF
 module TEST_CELL(input clk, input a, input b, output reg c);
 parameter PATH = "DEFAULT";
 always @(posedge clk) begin
@@ -11,14 +11,14 @@ end
 endmodule
 EOF
 
-import -sv <<EOF
+verific -sv <<EOF
 module top(input clk, input a, input b, output c, output d);
 	TEST_CELL  #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
 	TEST_CELL  #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
 endmodule
 EOF
 
-import -import top
+verific -import top
 hierarchy -top top
 stat
 select -assert-count 2 t:TEST_CELL