Update backends to avoid bits()

backends/btor/btor.cc

@@ -709,12 +709,13 @@ struct BtorWorker
 				}
 			}
 
-			Const initval;
+			Const::Builder initval_bits(GetSize(sig_q));
 			for (int i = 0; i < GetSize(sig_q); i++)
 				if (initbits.count(sig_q[i]))
-					initval.bits().push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
+					initval_bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
 				else
-					initval.bits().push_back(State::Sx);
+					initval_bits.push_back(State::Sx);
+			Const initval = initval_bits.build();
 
 			int nid_init_val = -1;
 
@@ -1043,10 +1044,11 @@ struct BtorWorker
 				{
 					if (bit.wire == nullptr)
 					{
-						Const c(bit.data);
+						Const::Builder c_bits;
-
+						c_bits.push_back(bit.data);
-						while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
+						while (i + GetSize(c_bits) < GetSize(sig) && sig[i + GetSize(c_bits)].wire == nullptr)
-							c.bits().push_back(sig[i+GetSize(c)].data);
+							c_bits.push_back(sig[i + GetSize(c_bits)].data);
+						Const c = c_bits.build();
 
 						if (consts.count(c) == 0) {
 							int sid = get_bv_sid(GetSize(c));

backends/cxxrtl/cxxrtl_backend.cc

@@ -1668,26 +1668,29 @@ struct CxxrtlWorker {
 						f << signal_temp << " == ";
 						dump_sigspec(compare, /*is_lhs=*/false, for_debug);
 					} else if (compare.is_fully_const()) {
-						RTLIL::Const compare_mask, compare_value;
+						RTLIL::Const::Builder compare_mask_builder(compare.size());
+						RTLIL::Const::Builder compare_value_builder(compare.size());
 						for (auto bit : compare.as_const()) {
 							switch (bit) {
 								case RTLIL::S0:
 								case RTLIL::S1:
-									compare_mask.bits().push_back(RTLIL::S1);
+									compare_mask_builder.push_back(RTLIL::S1);
-									compare_value.bits().push_back(bit);
+									compare_value_builder.push_back(bit);
 									break;
 
 								case RTLIL::Sx:
 								case RTLIL::Sz:
 								case RTLIL::Sa:
-									compare_mask.bits().push_back(RTLIL::S0);
+									compare_mask_builder.push_back(RTLIL::S0);
-									compare_value.bits().push_back(RTLIL::S0);
+									compare_value_builder.push_back(RTLIL::S0);
 									break;
 
 								default:
 									log_assert(false);
 							}
 						}
+						RTLIL::Const compare_mask = compare_mask_builder.build();
+						RTLIL::Const compare_value = compare_value_builder.build();
 						f << "and_uu<" << compare.size() << ">(" << signal_temp << ", ";
 						dump_const(compare_mask);
 						f << ") == ";
@@ -3042,7 +3045,7 @@ struct CxxrtlWorker {
 								if (init == RTLIL::Const()) {
 									init = RTLIL::Const(State::Sx, GetSize(bit.wire));
 								}
-								init.bits()[bit.offset] = port.init_value[i];
+								init.set(bit.offset, port.init_value[i]);
 							}
 						}
 					}

backends/functional/test_generic.cc

@@ -105,7 +105,7 @@ struct MemContentsTest {
 				RTLIL::Const values;
 				for(addr_t addr = low; addr <= high; addr++) {
 					RTLIL::Const word(data_dist(rnd), data_width);
-					values.bits().insert(values.bits().end(), word.begin(), word.end());
+					values.append(word);
 				}
 				insert_concatenated(low, values);
 			}

backends/simplec/simplec.cc

@@ -657,7 +657,7 @@ struct SimplecWorker
 			{
 				SigSpec sig = sigmaps.at(module)(w);
 				Const val = w->attributes.at(ID::init);
-				val.bits().resize(GetSize(sig), State::Sx);
+				val.resize(GetSize(sig), State::Sx);
 
 				for (int i = 0; i < GetSize(sig); i++)
 					if (val[i] == State::S0 || val[i] == State::S1) {

backends/smt2/smt2.cc

@@ -1079,14 +1079,14 @@ struct Smt2Worker
 
 				RTLIL::SigSpec sig = sigmap(wire);
 				Const val = wire->attributes.at(ID::init);
-				val.bits().resize(GetSize(sig), State::Sx);
+				val.resize(GetSize(sig), State::Sx);
 				if (bvmode && GetSize(sig) > 1) {
 					Const mask(State::S1, GetSize(sig));
 					bool use_mask = false;
 					for (int i = 0; i < GetSize(sig); i++)
 						if (val[i] != State::S0 && val[i] != State::S1) {
-							val.bits()[i] = State::S0;
+							val.set(i, State::S0);
-							mask.bits()[i] = State::S0;
+							mask.set(i, State::S0);
 							use_mask = true;
 						}
 					if (use_mask)
@@ -1361,10 +1361,10 @@ struct Smt2Worker
 					for (int k = 0; k < GetSize(initword); k++) {
 						if (initword[k] == State::S0 || initword[k] == State::S1) {
 							gen_init_constr = true;
-							initmask.bits()[k] = State::S1;
+							initmask.set(k, State::S1);
 						} else {
-							initmask.bits()[k] = State::S0;
+							initmask.set(k, State::S0);
-							initword.bits()[k] = State::S0;
+							initword.set(k, State::S0);
 						}
 					}
 

backends/verilog/verilog_backend.cc

@@ -327,19 +327,20 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 
 void dump_reg_init(std::ostream &f, SigSpec sig)
 {
-	Const initval;
 	bool gotinit = false;
 
+	Const::Builder initval_bits(sig.size());
 	for (auto bit : active_sigmap(sig)) {
 		if (active_initdata.count(bit)) {
-			initval.bits().push_back(active_initdata.at(bit));
+			initval_bits.push_back(active_initdata.at(bit));
 			gotinit = true;
 		} else {
-			initval.bits().push_back(State::Sx);
+			initval_bits.push_back(State::Sx);
 		}
 	}
 
 	if (gotinit) {
+		Const initval = initval_bits.build();
 		f << " = ";
 		dump_const(f, initval);
 	}
@@ -767,9 +768,10 @@ void dump_memory(std::ostream &f, std::string indent, Mem &mem)
 					dump_sigspec(os, port.data.extract(sub * mem.width, mem.width));
 					os << stringf(" = %s[", mem_id.c_str());;
 					if (port.wide_log2) {
-						Const addr_lo;
+						Const::Builder addr_lo_builder(port.wide_log2);
 						for (int i = 0; i < port.wide_log2; i++)
-							addr_lo.bits().push_back(State(sub >> i & 1));
+							addr_lo_builder.push_back(State(sub >> i & 1));
+						Const addr_lo = addr_lo_builder.build();
 						os << "{";
 						os << temp_id;
 						os << ", ";