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https://github.com/YosysHQ/yosys
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debug flag
This commit is contained in:
Alain Dargelas
parent
21f026cb05
commit
c8847e8286
1 changed files with 51 additions and 50 deletions
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@ -69,33 +69,36 @@ RTLIL::Wire *getParentWire(const RTLIL::SigSpec &sigspec)
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if (sigspec.empty()) {
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return nullptr; // Empty SigSpec, no parent wire
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}
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// Get the first SigBit
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const RTLIL::SigBit &first_bit = sigspec[0];
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// Return the parent wire
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return first_bit.wire;
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}
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void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout,
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RTLIL::Cell *cell, int fanout, int limit)
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RTLIL::Cell *cell, int fanout, int limit, bool debug)
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{
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if (fanout <= limit) {
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std::cout << "Nothing to do for: " << cell->name.c_str() << std::endl;
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std::cout << "Fanout: " << fanout << std::endl;
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if (debug) {
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std::cout << "Nothing to do for: " << cell->name.c_str() << std::endl;
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std::cout << "Fanout: " << fanout << std::endl;
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}
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return; // No need to insert buffers
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} else {
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std::cout << "Something to do for: " << cell->name.c_str() << std::endl;
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std::cout << "Fanout: " << fanout << std::endl;
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if (debug) {
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std::cout << "Something to do for: " << cell->name.c_str() << std::endl;
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std::cout << "Fanout: " << fanout << std::endl;
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}
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}
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sigmap.set(module);
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int num_buffers = std::min((int)std::ceil(static_cast<double>(fanout) / limit), limit);
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int max_output_per_buffer = std::ceil((float)fanout / (float)num_buffers);
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std::cout << "fanout: " << fanout << "\n";
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std::cout << "limit: " << limit << "\n";
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std::cout << "num_buffers: " << num_buffers << "\n";
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std::cout << "max_output_per_buffer: " << max_output_per_buffer << "\n";
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std::cout << "CELL: " << cell->name.c_str() << "\n" << std::flush;
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if (debug) {
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std::cout << "fanout: " << fanout << "\n";
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std::cout << "limit: " << limit << "\n";
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std::cout << "num_buffers: " << num_buffers << "\n";
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std::cout << "max_output_per_buffer: " << max_output_per_buffer << "\n";
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std::cout << "CELL: " << cell->name.c_str() << "\n" << std::flush;
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}
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// Get cell output
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RTLIL::SigSpec cellOutSig;
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@ -109,7 +112,7 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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}
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// Create buffers and new wires
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std::map<Cell *, int> bufferActualFanout;
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std::map<Cell *, int> bufferActualFanout; // Keep track of the fanout count for each new buffer
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std::map<RTLIL::SigSpec, std::vector<std::tuple<RTLIL::SigSpec, Cell *>>> buffer_outputs;
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std::map<SigSpec, int> bufferIndexes;
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for (SigChunk chunk : cellOutSig.chunks()) {
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@ -138,38 +141,39 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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// Fix input connections to cells in fanout of buffer to point to the inserted buffer
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for (Cell *c : cells) {
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std::cout << "\n CELL in fanout: " << c->name.c_str() << "\n" << std::flush;
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if (debug)
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std::cout << "\n CELL in fanout: " << c->name.c_str() << "\n" << std::flush;
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for (auto &conn : c->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = sigmap(conn.second);
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if (c->input(portName)) {
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if (actual.is_chunk()) {
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if (debug)
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std::cout << " IS A CHUNK" << std::endl;
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if (buffer_outputs.find(actual) != buffer_outputs.end()) {
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std::cout << " CHUNK, indexCurrentBuffer: " << bufferIndexes[actual] << " buffer_outputs "
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if (debug) std::cout << " CHUNK, indexCurrentBuffer: " << bufferIndexes[actual] << " buffer_outputs "
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<< buffer_outputs[actual].size() << std::endl;
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>> &buf_info_vec = buffer_outputs[actual];
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int bufferIndex = bufferIndexes[actual];
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std::cout << " BUFFER INDEX: " << bufferIndex << std::endl;
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std::cout << " VEC SIZE: " << buf_info_vec.size() << std::endl;
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std::tuple<RTLIL::SigSpec, Cell *> &buf_info = buf_info_vec[bufferIndex];
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SigSpec newSig = std::get<0>(buf_info);
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Cell *newBuf = std::get<1>(buf_info);
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std::cout << " MATCH" << std::endl;
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c->setPort(portName, newSig);
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sig2CellsInFanout[newSig].insert(c);
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bufferActualFanout[newBuf]++;
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std::cout << " b: " << newBuf->name.c_str() << " fanout: " << bufferActualFanout[newBuf]
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<< std::endl;
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if (debug)std::cout << " USE: " << newBuf->name.c_str() << " fanout: " << bufferActualFanout[newBuf]
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<< std::endl;
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if (bufferActualFanout[newBuf] >= max_output_per_buffer) {
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std::cout << " REACHED MAX" << std::endl;
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if (debug) std::cout << " REACHED MAX" << std::endl;
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if (buffer_outputs[actual].size() - 1 > bufferIndex) {
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bufferIndexes[actual]++;
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std::cout << " NEXT BUFFER" << std::endl;
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if (debug) std::cout << " NEXT BUFFER" << std::endl;
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}
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}
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}
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} else {
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std::cout << " NOT CHUNK" << std::endl;
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if (debug)
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std::cout << " NOT A CHUNK" << std::endl;
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bool match = false;
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for (SigChunk chunk_a : actual.chunks()) {
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if (sigmap(SigSpec(chunk_a)) == sigmap(SigSpec(cellOutSig))) {
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@ -186,34 +190,29 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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break;
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}
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if (match) {
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std::cout << " MATCH" << std::endl;
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if (debug) std::cout << " MATCH" << std::endl;
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std::vector<RTLIL::SigChunk> newChunks;
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bool missed = true;
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for (SigChunk chunk : actual.chunks()) {
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bool replaced = false;
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if (buffer_outputs.find(chunk) != buffer_outputs.end()) {
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std::cout << " CHUNK, indexCurrentBuffer: " << bufferIndexes[chunk]
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if (debug) std::cout << " CHUNK, indexCurrentBuffer: " << bufferIndexes[chunk]
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<< " buffer_outputs " << buffer_outputs[chunk].size() << std::endl;
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>> &buf_info_vec = buffer_outputs[chunk];
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int bufferIndex = bufferIndexes[chunk];
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std::cout << " BUFFER INDEX: " << bufferIndex << std::endl;
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std::cout << " VEC SIZE: " << buf_info_vec.size() << std::endl;
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std::tuple<RTLIL::SigSpec, Cell *> &buf_info = buf_info_vec[bufferIndex];
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SigSpec newSig = std::get<0>(buf_info);
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Cell *newBuf = std::get<1>(buf_info);
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missed = false;
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newChunks.push_back(newSig.as_chunk());
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sig2CellsInFanout[newSig].insert(c);
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replaced = true;
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bufferActualFanout[newBuf]++;
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std::cout << " b: " << newBuf->name.c_str()
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if (debug) std::cout << " USE: " << newBuf->name.c_str()
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<< " fanout: " << bufferActualFanout[newBuf] << std::endl;
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if (bufferActualFanout[newBuf] >= max_output_per_buffer) {
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std::cout << " REACHED MAX" << std::endl;
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if (debug) std::cout << " REACHED MAX" << std::endl;
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if (buffer_outputs[chunk].size() - 1 > bufferIndex) {
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bufferIndexes[chunk]++;
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std::cout << " NEXT BUFFER" << std::endl;
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if (debug) std::cout << " NEXT BUFFER" << std::endl;
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}
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}
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}
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@ -221,9 +220,6 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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newChunks.push_back(chunk);
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}
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}
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if (missed) {
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exit(1);
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}
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c->setPort(portName, newChunks);
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break;
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}
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@ -232,24 +228,21 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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}
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}
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// Recursively fix the fanout of the newly created buffers
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for (std::map<Cell *, int>::iterator itr = bufferActualFanout.begin(); itr != bufferActualFanout.end(); itr++) {
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if (itr->second == 1) {
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std::cout << "Buffer with fanout 1: " << itr->first->name.c_str() << std::endl;
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// Remove previously inserted buffers with fanout of 1 (Hard to predict the last buffer usage in above step)
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if (debug) std::cout << "Buffer with fanout 1: " << itr->first->name.c_str() << std::endl;
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RTLIL::SigSpec bufferInSig = itr->first->getPort(ID::A);
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RTLIL::SigSpec bufferOutSig = itr->first->getPort(ID::Y);
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// std::cout << "bufferOutSig: " << bufferOutSig.as_wire()->name.c_str()
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// << " bufferInSig: " << bufferInSig.as_wire()->name.c_str() << std::endl;
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// Remove newly created buffers with a fanout of 1
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for (Cell *c : cells) {
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std::cout << "Cell in its fanout: " << c->name.c_str() << std::endl;
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if (debug) std::cout << "Cell in its fanout: " << c->name.c_str() << std::endl;
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for (auto &conn : c->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (c->input(portName)) {
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if (actual.is_chunk()) {
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if (bufferOutSig == sigmap(actual)) {
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std::cout << "Replace1: " << getParentWire(bufferOutSig)->name.c_str() << " by "
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if (debug) std::cout << "Replace: " << getParentWire(bufferOutSig)->name.c_str() << " by "
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<< getParentWire(bufferInSig)->name.c_str() << std::endl;
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c->setPort(portName, bufferInSig);
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}
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@ -257,7 +250,7 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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std::vector<RTLIL::SigChunk> newChunks;
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for (SigChunk chunk : actual.chunks()) {
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if (sigmap(SigSpec(chunk)) == sigmap(bufferOutSig)) {
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std::cout << "Replace2: " << getParentWire(bufferOutSig)->name.c_str()
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if (debug) std::cout << "Replace: " << getParentWire(bufferOutSig)->name.c_str()
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<< " by " << getParentWire(bufferInSig)->name.c_str() << std::endl;
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newChunks.push_back(bufferInSig.as_chunk());
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} else {
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@ -272,7 +265,8 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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module->remove(itr->first);
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module->remove({bufferOutSig.as_wire()});
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} else {
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fixfanout(design, module, sigmap, sig2CellsInFanout, itr->first, itr->second, limit);
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// Recursively fix the fanout of the newly created buffers
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fixfanout(design, module, sigmap, sig2CellsInFanout, itr->first, itr->second, limit, debug);
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}
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}
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}
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@ -334,7 +328,7 @@ void calculateFanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
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}
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}
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std::string substringUntil(const std::string &str, char delimiter)
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std::string substringuntil(const std::string &str, char delimiter)
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{
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size_t pos = str.find(delimiter);
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if (pos != std::string::npos) {
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@ -352,6 +346,7 @@ struct AnnotateCellFanout : public ScriptPass {
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{
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int limit = -1;
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bool formalFriendly = false;
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bool debug = false;
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if (design == nullptr) {
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log_error("No design object\n");
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return;
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@ -361,6 +356,10 @@ struct AnnotateCellFanout : public ScriptPass {
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-debug") {
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debug = true;
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continue;
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}
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if (args[argidx] == "-limit") {
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limit = std::atoi(args[++argidx].c_str());
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continue;
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@ -407,11 +406,13 @@ struct AnnotateCellFanout : public ScriptPass {
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}
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}
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std::string parent = getParentWire(cellOutSig)->name.c_str();
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parent = substringUntil(parent, '[');
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parent = substringuntil(parent, '[');
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if (netsToSplitS.find(parent) == netsToSplitS.end()) {
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netsToSplit += std::string(" w:") + parent; // Wire
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portsToSplit += std::string(" o:") + parent; // Port
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portsToSplit += std::string(" o:") + parent; // Output port
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netsToSplitS.insert(parent);
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// Splitnets has to be invoke with individual nets, sending a bunch of nets as selection
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// selects more than required (bug in selection/splitnets).
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std::string splitnets = std::string("splitnets ") + netsToSplit;
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Pass::call(design, splitnets);
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splitnets = std::string("splitnets -ports_only ") + portsToSplit;
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@ -437,7 +438,7 @@ struct AnnotateCellFanout : public ScriptPass {
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Cell *cell = itrCell.first;
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int fanout = itrCell.second;
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if (limit > 0 && (fanout > limit)) {
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fixfanout(design, module, sigmap, sig2CellsInFanout, cell, fanout, limit);
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fixfanout(design, module, sigmap, sig2CellsInFanout, cell, fanout, limit, debug);
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fixedFanout = true;
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} else {
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// Add attribute with fanout info to every cell
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