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Added $div and $mod technology mapping
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4 changed files with 134 additions and 31 deletions
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@ -968,7 +968,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (width > width_hint && width_hint > 0)
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width = width_hint;
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if (width < width_hint) {
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if (type == AST_ADD || type == AST_SUB)
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if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
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width++;
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if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
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width = width_hint;
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