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Added tests/simple/repwhile.v

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Clifford Wolf 2014-06-06 17:47:20 +02:00
parent ab54ce17c8
commit c82db39935
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module test001(output [63:0] y);
function [7:0] mylog2;
input [31:0] value;
begin
mylog2 = 0;
while (value > 0) begin
value = value >> 1;
mylog2 = mylog2 + 1;
end
end
endfunction
genvar i;
generate
for (i = 0; i < 64; i = i+1) begin
localparam tmp = mylog2(i);
assign y[i] = tmp;
end
endgenerate
endmodule