mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 13:29:12 +00:00 
			
		
		
		
	Fixed "share" for memory read ports
This commit is contained in:
		
							parent
							
								
									358bf70a21
								
							
						
					
					
						commit
						c7f99be3be
					
				
					 1 changed files with 7 additions and 0 deletions
				
			
		| 
						 | 
				
			
			@ -419,6 +419,13 @@ struct ShareWorker
 | 
			
		|||
			return supercell;
 | 
			
		||||
		}
 | 
			
		||||
 | 
			
		||||
		if (c1->type == "$memrd")
 | 
			
		||||
		{
 | 
			
		||||
			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
 | 
			
		||||
			module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA"));
 | 
			
		||||
			return supercell;
 | 
			
		||||
		}
 | 
			
		||||
 | 
			
		||||
		log_abort();
 | 
			
		||||
	}
 | 
			
		||||
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue