mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-11 00:23:26 +00:00
Code Activity

Fixed "share" for memory read ports

Browse source
This commit is contained in:
Clifford Wolf 2014-08-03 20:19:50 +02:00
parent 358bf70a21
commit c7f99be3be
1 changed files with 7 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

7
passes/sat/share.cc
View file

@ -419,6 +419,13 @@ struct ShareWorker
return supercell; return supercell;
} }
if (c1->type == "$memrd")
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
module->connect(c2->getPort("\\DATA"), supercell->getPort("\\DATA"));
return supercell;
}
log_abort(); log_abort();
} }