mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 22:23:23 +00:00
Bugfix in "read_verilog -D NAME=VAL" handling
This commit is contained in:
parent
c17d98f55c
commit
c7f6fb6e17
1 changed files with 3 additions and 3 deletions
|
@ -303,10 +303,10 @@ struct VerilogFrontend : public Frontend {
|
||||||
}
|
}
|
||||||
if (arg == "-D" && argidx+1 < args.size()) {
|
if (arg == "-D" && argidx+1 < args.size()) {
|
||||||
std::string name = args[++argidx], value;
|
std::string name = args[++argidx], value;
|
||||||
size_t equal = name.find('=', 2);
|
size_t equal = name.find('=');
|
||||||
if (equal != std::string::npos) {
|
if (equal != std::string::npos) {
|
||||||
value = arg.substr(equal+1);
|
value = name.substr(equal+1);
|
||||||
name = arg.substr(0, equal);
|
name = name.substr(0, equal);
|
||||||
}
|
}
|
||||||
defines_map[name] = value;
|
defines_map[name] = value;
|
||||||
continue;
|
continue;
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue