From c7f66737aaf29133c6a095fb1efca881e292c22f Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Thu, 9 May 2024 06:36:02 -0700 Subject: [PATCH] Fix Yosys to allow SV again --- frontends/verific/verific.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fa1a21e54..9fae77e54 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3397,6 +3397,7 @@ struct VerificPass : public Pass { // Treat .v as SystemVerilog too (overriding default behavior to treat it as VERILOG_2000) hdl_file_sort::RemoveFileExt(".v"); hdl_file_sort::AddFileExtMode(".v", veri_file::SYSTEM_VERILOG); + hdl_file_sort::AddFileExtMode(".sv", veri_file::SYSTEM_VERILOG); // Select analyze function auto analyze_function = (args[argidx] == "-auto_discover") ? hdl_file_sort::AnalyzeDiscoveredFiles : hdl_file_sort::AnalyzeSortedFiles;