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https://github.com/YosysHQ/yosys
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Remove .c_str() from stringf parameters
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parent
c41ba912d8
commit
c7df6954b9
90 changed files with 773 additions and 773 deletions
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@ -188,12 +188,12 @@ struct SynthIntelPass : public ScriptPass {
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{
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if (check_label("begin")) {
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if (check_label("family"))
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run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
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run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt));
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// Misc and common cells
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run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
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run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
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}
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if (check_label("coarse")) {
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@ -225,7 +225,7 @@ struct SynthIntelPass : public ScriptPass {
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run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL9X9");
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run("chtype -set $mul t:$__soft_mul");
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run("alumacc");
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run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt.c_str()));
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run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt));
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} else {
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run("alumacc");
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}
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@ -274,7 +274,7 @@ struct SynthIntelPass : public ScriptPass {
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if (check_label("map_cells")) {
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if (iopads || help_mode)
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run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
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run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
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run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt));
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run("clean -purge");
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}
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@ -294,7 +294,7 @@ struct SynthIntelPass : public ScriptPass {
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if (check_label("vpr")) {
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if (!blif_file.empty() || help_mode) {
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run(stringf("opt_clean -purge"));
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run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
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run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file));
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}
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}
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}
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