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Remove .c_str() from stringf parameters

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This commit is contained in:
Robert O'Callahan 2025-08-19 22:45:26 +00:00
parent c41ba912d8
commit c7df6954b9
90 changed files with 773 additions and 773 deletions
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66
passes/tests/test_autotb.cc
View file

@ -114,7 +114,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
if (wire->port_output) {
count_ports++;
signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()));
} else if (wire->port_input) {
count_ports++;
bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock);
@ -134,73 +134,73 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
if (wire->attributes.count(ID::gentb_constant) != 0)
signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string();
}
f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()));
}
}
f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
f << stringf("%s %s(\n", id(mod->name.str()), idy("uut", mod->name.str()));
for (auto wire : mod->wires()) {
if (wire->port_output || wire->port_input)
f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
f << stringf("\t.%s(%s)%s\n", id(wire->name.str()),
idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : "");
}
f << stringf(");\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "reset").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "reset"));
f << stringf("begin\n");
int delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d 0;\n", it->first, ++delay_counter*2);
for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it)
f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d 0;\n", it->first, ++delay_counter*2);
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
f << stringf("\t#100; %s <= 1;\n", it->first);
f << stringf("\t#100; %s <= 0;\n", it->first);
}
delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
f << stringf("\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d ~0;\n", it->first, ++delay_counter*2);
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
f << stringf("\t#100; %s <= 1;\n", it->first);
f << stringf("\t#100; %s <= 0;\n", it->first);
}
delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); ++it) {
if (signal_const.count(it->first) == 0)
continue;
f << stringf("\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str());
f << stringf("\t%s <= #%d 'b%s;\n", it->first, ++delay_counter*2, signal_const[it->first]);
}
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "update_data").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "update_data"));
f << stringf("begin\n");
delay_counter = 0;
for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
if (signal_const.count(it->first) > 0)
continue;
f << stringf("\txorshift128;\n");
f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2);
f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first, ++delay_counter*2);
}
f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "update_clock").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "update_clock"));
f << stringf("begin\n");
if (signal_clk.size()) {
f << stringf("\txorshift128;\n");
f << stringf("\t{");
int total_clock_bits = 0;
for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first);
total_clock_bits += it->second;
}
f << stringf(" } = {");
for (auto it = signal_clk.begin(); it != signal_clk.end(); it++)
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first);
f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits + 1);
}
f << stringf("end\n");
@ -210,12 +210,12 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
std::vector<std::string> header1;
std::string header2 = "";
f << stringf("task %s;\n", idy(mod->name.str(), "print_status").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "print_status"));
f << stringf("begin\n");
f << stringf("\t$fdisplay(file, \"#OUT# %%b %%b %%b %%t %%d\", {");
if (signal_in.size())
for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first);
int len = it->second;
header2 += ", \"";
if (len > 1)
@ -237,7 +237,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
header2 += ", \" \"";
if (signal_clk.size()) {
for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first);
int len = it->second;
header2 += ", \"";
if (len > 1)
@ -259,7 +259,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
header2 += ", \" \"";
if (signal_out.size()) {
for (auto it = signal_out.begin(); it != signal_out.end(); it++) {
f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str());
f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first);
int len = it->second;
header2 += ", \"";
if (len > 1)
@ -281,25 +281,25 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "print_header").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "print_header"));
f << stringf("begin\n");
f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
for (auto &hdr : header1)
f << stringf("\t$fdisplay(file, \"#OUT# %s\");\n", hdr.c_str());
f << stringf("\t$fdisplay(file, \"#OUT# %s\");\n", hdr);
f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2.c_str());
f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2);
f << stringf("end\n");
f << stringf("endtask\n\n");
f << stringf("task %s;\n", idy(mod->name.str(), "test").c_str());
f << stringf("task %s;\n", idy(mod->name.str(), "test"));
f << stringf("begin\n");
f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
f << stringf("\t%s;\n", idy(mod->name.str(), "reset").c_str());
f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()));
f << stringf("\t%s;\n", idy(mod->name.str(), "reset"));
f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header"));
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data"));
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock"));
f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status"));
f << stringf("\tend\n");
f << stringf("end\n");
f << stringf("endtask\n\n");
@ -317,7 +317,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
f << stringf("\tend\n");
for (auto module : design->modules())
if (!module->get_bool_attribute(ID::gentb_skip))
f << stringf("\t%s;\n", idy(module->name.str(), "test").c_str());
f << stringf("\t%s;\n", idy(module->name.str(), "test"));
f << stringf("\t$fclose(file);\n");
f << stringf("\t$finish;\n");
f << stringf("end\n\n");

26
passes/tests/test_cell.cc
View file

@ -591,7 +591,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
if (vlog_file.is_open())
{
vlog_file << stringf("\nmodule %s;\n", uut_name.c_str());
vlog_file << stringf("\nmodule %s;\n", uut_name);
for (auto port : gold_mod->ports) {
RTLIL::Wire *wire = gold_mod->wire(port);
@ -601,13 +601,13 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
vlog_file << stringf(" wire [%d:0] %s_expr, %s_noexpr;\n", GetSize(wire)-1, log_id(wire), log_id(wire));
}
vlog_file << stringf(" %s_expr uut_expr(", uut_name.c_str());
vlog_file << stringf(" %s_expr uut_expr(", uut_name);
for (int i = 0; i < GetSize(gold_mod->ports); i++)
vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr");
vlog_file << stringf(");\n");
vlog_file << stringf(" %s_expr uut_noexpr(", uut_name.c_str());
vlog_file << stringf(" %s_expr uut_noexpr(", uut_name);
for (int i = 0; i < GetSize(gold_mod->ports); i++)
vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr");
@ -615,7 +615,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
vlog_file << stringf(" task run;\n");
vlog_file << stringf(" begin\n");
vlog_file << stringf(" $display(\"%s\");\n", uut_name.c_str());
vlog_file << stringf(" $display(\"%s\");\n", uut_name);
}
for (int i = 0; i < 64; i++)
@ -662,7 +662,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
gate_ce.set(gate_wire, in_value);
if (vlog_file.is_open() && GetSize(in_value) > 0) {
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string());
if (!vlog_pattern_info.empty())
vlog_pattern_info += " ";
vlog_pattern_info += stringf("%s=%s", log_id(gold_wire), log_signal(in_value));
@ -716,8 +716,8 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
if (vlog_file.is_open()) {
vlog_file << stringf(" $display(\"[%s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n",
vlog_pattern_info.c_str(), log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire));
vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string());
vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string());
}
}
@ -1142,12 +1142,12 @@ struct TestCellPass : public Pass {
else
uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
if (!write_prefix.empty()) {
Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i));
Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i));
} else if (edges) {
Pass::call(design, "dump gold");
run_edges_test(design, verbose);
} else {
Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..", techmap_cmd.c_str()));
Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..", techmap_cmd));
if (!noopt)
Pass::call(design, "opt -fast gate");
if (!nosat)
@ -1157,11 +1157,11 @@ struct TestCellPass : public Pass {
Pass::call(design, "dump gold");
if (!nosat)
Pass::call(design, "sat -verify -enable_undef -prove trigger 0 -show-inputs -show-outputs miter");
std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1).c_str(), i);
std::string uut_name = stringf("uut_%s_%d", cell_type.substr(1), i);
if (vlog_file.is_open()) {
Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name.c_str(), uut_name.c_str()));
Pass::call(design, stringf("copy gold %s_expr; select %s_expr", uut_name, uut_name));
Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected");
Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name.c_str(), uut_name.c_str()));
Pass::call(design, stringf("copy gold %s_noexpr; select %s_noexpr", uut_name, uut_name));
Backend::backend_call(design, &vlog_file, "<test_cell -vlog>", "verilog -selected -noexpr");
uut_names.push_back(uut_name);
}
@ -1208,7 +1208,7 @@ struct TestCellPass : public Pass {
if (vlog_file.is_open()) {
vlog_file << "\nmodule testbench;\n";
for (auto &uut : uut_names)
vlog_file << stringf(" %s %s ();\n", uut.c_str(), uut.c_str());
vlog_file << stringf(" %s %s ();\n", uut, uut);
vlog_file << " initial begin\n";
for (auto &uut : uut_names)
vlog_file << " " << uut << ".run;\n";