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https://github.com/YosysHQ/yosys
synced 2025-09-13 05:01:29 +00:00
Remove .c_str() from stringf parameters
This commit is contained in:
parent
c41ba912d8
commit
c7df6954b9
90 changed files with 773 additions and 773 deletions
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@ -33,8 +33,8 @@ FstData::FstData(std::string filename) : ctx(nullptr)
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std::string filename_trim = file_base_name(filename);
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if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vcd") == 0) {
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filename_trim.erase(filename_trim.size()-4);
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tmp_file = stringf("%s/converted_%s.fst", get_base_tmpdir().c_str(), filename_trim.c_str());
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std::string cmd = stringf("vcd2fst %s %s", filename.c_str(), tmp_file.c_str());
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tmp_file = stringf("%s/converted_%s.fst", get_base_tmpdir(), filename_trim);
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std::string cmd = stringf("vcd2fst %s %s", filename, tmp_file);
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log("Exec: %s\n", cmd.c_str());
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if (run_command(cmd) != 0)
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log_cmd_error("Shell command failed!\n");
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@ -307,7 +307,7 @@ bool is_absolute_path(std::string filename)
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void remove_directory(std::string dirname)
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{
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#ifdef _WIN32
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run_command(stringf("rmdir /s /q \"%s\"", dirname.c_str()));
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run_command(stringf("rmdir /s /q \"%s\"", dirname));
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#else
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struct stat stbuf;
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struct dirent **namelist;
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@ -315,7 +315,7 @@ void remove_directory(std::string dirname)
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log_assert(n >= 0);
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for (int i = 0; i < n; i++) {
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if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) {
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std::string buffer = stringf("%s/%s", dirname.c_str(), namelist[i]->d_name);
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std::string buffer = stringf("%s/%s", dirname, namelist[i]->d_name);
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if (!stat(buffer.c_str(), &stbuf) && S_ISREG(stbuf.st_mode)) {
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remove(buffer.c_str());
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} else
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@ -791,7 +791,7 @@ dict<std::string, std::pair<std::string, int>> get_coverage_data()
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dict<std::string, std::pair<std::string, int>> coverage_data;
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for (auto &it : pass_register) {
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std::string key = stringf("passes.%s", it.first.c_str());
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std::string key = stringf("passes.%s", it.first);
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coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__);
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coverage_data[key].second += it.second->call_counter;
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}
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@ -900,7 +900,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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if (width)
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{
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SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid.c_str(), idx), width);
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SigSpec sig_q = module->addWire(stringf("$%s$rdreg[%d]$q", memid, idx), width);
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SigSpec sig_d;
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int pos = 0;
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@ -910,7 +910,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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port.addr[i] = sig_q[pos++];
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}
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c = module->addDff(stringf("$%s$rdreg[%d]", memid.c_str(), idx), port.clk, sig_d, sig_q, port.clk_polarity);
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c = module->addDff(stringf("$%s$rdreg[%d]", memid, idx), port.clk, sig_d, sig_q, port.clk_polarity);
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} else {
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c = nullptr;
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}
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@ -919,7 +919,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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{
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log_assert(port.arst == State::S0 || port.srst == State::S0);
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SigSpec async_d = module->addWire(stringf("$%s$rdreg[%d]$d", memid.c_str(), idx), GetSize(port.data));
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SigSpec async_d = module->addWire(stringf("$%s$rdreg[%d]$d", memid, idx), GetSize(port.data));
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SigSpec sig_d = async_d;
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for (int i = 0; i < GetSize(wr_ports); i++) {
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@ -942,7 +942,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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raddr = port.sub_addr(sub);
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SigSpec addr_eq;
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if (raddr != waddr)
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addr_eq = module->Eq(stringf("$%s$rdtransen[%d][%d][%d]$d", memid.c_str(), idx, i, sub), raddr, waddr);
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addr_eq = module->Eq(stringf("$%s$rdtransen[%d][%d][%d]$d", memid, idx, i, sub), raddr, waddr);
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int pos = 0;
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int ewidth = width << min_wide_log2;
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int wsub = wide_write ? sub : 0;
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@ -955,10 +955,10 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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SigSpec other = port.transparency_mask[i] ? wport.data.extract(pos + wsub * width, epos-pos) : Const(State::Sx, epos-pos);
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SigSpec cond;
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if (raddr != waddr)
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cond = module->And(stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid.c_str(), idx, i, sub, pos), wport.en[pos + wsub * width], addr_eq);
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cond = module->And(stringf("$%s$rdtransgate[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), wport.en[pos + wsub * width], addr_eq);
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else
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cond = wport.en[pos + wsub * width];
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SigSpec merged = module->Mux(stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid.c_str(), idx, i, sub, pos), cur, other, cond);
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SigSpec merged = module->Mux(stringf("$%s$rdtransmux[%d][%d][%d][%d]$d", memid, idx, i, sub, pos), cur, other, cond);
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sig_d.replace(pos + rsub * width, merged);
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pos = epos;
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}
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@ -966,7 +966,7 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) {
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}
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}
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IdString name = stringf("$%s$rdreg[%d]", memid.c_str(), idx);
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IdString name = stringf("$%s$rdreg[%d]", memid, idx);
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FfData ff(module, initvals, name);
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ff.width = GetSize(port.data);
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ff.has_clk = true;
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@ -2773,7 +2773,7 @@ RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
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}
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while (1) {
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RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
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RTLIL::IdString new_name = stringf("%s_%d", name, index);
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if (count_id(new_name) == 0)
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return new_name;
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index++;
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@ -103,7 +103,7 @@ struct SatGen
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} else {
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std::string wire_name = RTLIL::unescape_id(bit.wire->name);
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std::string name = pf +
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(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name.c_str(), bit.offset));
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(bit.wire->width == 1 ? wire_name : stringf("%s [%d]", wire_name, bit.offset));
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vec.push_back(ez->frozen_literal(name));
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imported_signals[pf][bit] = vec.back();
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}
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@ -89,7 +89,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a
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if (Tcl_GetCommandInfo(interp, tcl_command_name.c_str(), &info) != 0) {
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log("[TCL: yosys -import] Command name collision: found pre-existing command `%s' -> skip.\n", it.first.c_str());
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} else {
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std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name.c_str(), it.first.c_str());
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std::string tcl_script = stringf("proc %s args { yosys %s {*}$args }", tcl_command_name, it.first);
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Tcl_Eval(interp, tcl_script.c_str());
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}
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}
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@ -287,7 +287,7 @@ RTLIL::IdString new_id(std::string file, int line, std::string func)
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if (pos != std::string::npos)
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func = func.substr(pos+1);
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return stringf("$auto$%s:%d:%s$%d", file.c_str(), line, func.c_str(), autoidx++);
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return stringf("$auto$%s:%d:%s$%d", file, line, func, autoidx++);
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}
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RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std::string suffix)
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@ -304,7 +304,7 @@ RTLIL::IdString new_id_suffix(std::string file, int line, std::string func, std:
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if (pos != std::string::npos)
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func = func.substr(pos+1);
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return stringf("$auto$%s:%d:%s$%s$%d", file.c_str(), line, func.c_str(), suffix.c_str(), autoidx++);
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return stringf("$auto$%s:%d:%s$%s$%d", file, line, func, suffix, autoidx++);
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}
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RTLIL::Design *yosys_get_design()
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@ -320,7 +320,7 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
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str += stringf("(%d) ", recursion_counter);
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str += "yosys";
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if (!design->selected_active_module.empty())
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str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str());
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str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module));
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if (!design->full_selection()) {
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if (design->selected_active_module.empty())
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str += "*";
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