mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
Add new $check cell to represent assertions with a message.
This commit is contained in:
Catherine
Jannis Harder
parent
e1a59ba80b
commit
c7bf0e3b8f
12 changed files with 516 additions and 306 deletions
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@ -218,7 +218,7 @@ bool is_internal_cell(RTLIL::IdString type)
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bool is_effectful_cell(RTLIL::IdString type)
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{
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return type.isPublic() || type == ID($print);
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return type.in(ID($print), ID($check));
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}
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bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
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@ -282,7 +282,7 @@ struct FlowGraph {
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CONNECT,
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CELL_SYNC,
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CELL_EVAL,
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PRINT_SYNC,
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EFFECT_SYNC,
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PROCESS_SYNC,
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PROCESS_CASE,
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MEM_RDPORT,
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@ -292,7 +292,7 @@ struct FlowGraph {
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Type type;
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RTLIL::SigSig connect = {};
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const RTLIL::Cell *cell = nullptr;
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std::vector<const RTLIL::Cell*> print_sync_cells;
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std::vector<const RTLIL::Cell*> cells;
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const RTLIL::Process *process = nullptr;
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const Mem *mem = nullptr;
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int portidx;
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@ -480,11 +480,11 @@ struct FlowGraph {
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return node;
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}
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Node *add_print_sync_node(std::vector<const RTLIL::Cell*> cells)
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Node *add_effect_sync_node(std::vector<const RTLIL::Cell*> cells)
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{
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Node *node = new Node;
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node->type = Node::Type::PRINT_SYNC;
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node->print_sync_cells = cells;
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node->type = Node::Type::EFFECT_SYNC;
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node->cells = cells;
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nodes.push_back(node);
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return node;
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}
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@ -1063,99 +1063,6 @@ struct CxxrtlWorker {
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f << ".val()";
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}
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void dump_print(const RTLIL::Cell *cell)
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{
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Fmt fmt = {};
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fmt.parse_rtlil(cell);
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << " == value<1>{1u}) {\n";
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inc_indent();
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dict<std::string, RTLIL::SigSpec> fmt_args;
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f << indent << "struct : public lazy_fmt {\n";
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inc_indent();
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f << indent << "std::string operator() () const override {\n";
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inc_indent();
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fmt.emit_cxxrtl(f, indent, [&](const RTLIL::SigSpec &sig) {
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if (sig.size() == 0)
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f << "value<0>()";
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else {
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std::string arg_name = "arg" + std::to_string(fmt_args.size());
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fmt_args[arg_name] = sig;
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f << arg_name;
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}
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}, "performer");
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dec_indent();
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f << indent << "}\n";
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f << indent << "struct performer *performer;\n";
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for (auto arg : fmt_args)
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f << indent << "value<" << arg.second.size() << "> " << arg.first << ";\n";
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dec_indent();
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f << indent << "} formatter;\n";
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f << indent << "formatter.performer = performer;\n";
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for (auto arg : fmt_args) {
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f << indent << "formatter." << arg.first << " = ";
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dump_sigspec_rhs(arg.second);
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f << ";\n";
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}
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f << indent << "if (performer) {\n";
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inc_indent();
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f << indent << "static const metadata_map attributes = ";
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dump_metadata_map(cell->attributes);
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f << ";\n";
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f << indent << "performer->on_print(formatter, attributes);\n";
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dec_indent();
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f << indent << "} else {\n";
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inc_indent();
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f << indent << print_output << " << formatter();\n";
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dec_indent();
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f << indent << "}\n";
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dec_indent();
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f << indent << "}\n";
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}
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void dump_sync_print(std::vector<const RTLIL::Cell*> &cells)
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{
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log_assert(!cells.empty());
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const auto &trg = cells[0]->getPort(ID::TRG);
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const auto &trg_polarity = cells[0]->getParam(ID::TRG_POLARITY);
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f << indent << "if (";
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for (int i = 0; i < trg.size(); i++) {
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RTLIL::SigBit trg_bit = trg[i];
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trg_bit = sigmaps[trg_bit.wire->module](trg_bit);
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log_assert(trg_bit.wire);
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if (i != 0)
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f << " || ";
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if (trg_polarity[i] == State::S1)
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f << "posedge_";
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else
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f << "negedge_";
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f << mangle(trg_bit);
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}
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f << ") {\n";
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inc_indent();
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std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
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return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int();
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});
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for (auto cell : cells) {
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log_assert(cell->getParam(ID::TRG_ENABLE).as_bool());
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log_assert(cell->getPort(ID::TRG) == trg);
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log_assert(cell->getParam(ID::TRG_POLARITY) == trg_polarity);
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std::vector<const RTLIL::Cell*> inlined_cells;
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collect_cell_eval(cell, /*for_debug=*/false, inlined_cells);
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dump_inlined_cells(inlined_cells);
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dump_print(cell);
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}
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dec_indent();
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f << indent << "}\n";
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}
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void dump_inlined_cells(const std::vector<const RTLIL::Cell*> &cells)
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{
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if (cells.empty()) {
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@ -1309,6 +1216,144 @@ struct CxxrtlWorker {
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}
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}
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void dump_print(const RTLIL::Cell *cell)
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{
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Fmt fmt;
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fmt.parse_rtlil(cell);
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << " == value<1>{1u}) {\n";
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inc_indent();
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dict<std::string, RTLIL::SigSpec> fmt_args;
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f << indent << "struct : public lazy_fmt {\n";
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inc_indent();
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f << indent << "std::string operator() () const override {\n";
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inc_indent();
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fmt.emit_cxxrtl(f, indent, [&](const RTLIL::SigSpec &sig) {
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if (sig.size() == 0)
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f << "value<0>()";
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else {
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std::string arg_name = "arg" + std::to_string(fmt_args.size());
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fmt_args[arg_name] = sig;
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f << arg_name;
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}
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}, "performer");
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dec_indent();
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f << indent << "}\n";
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f << indent << "struct performer *performer;\n";
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for (auto arg : fmt_args)
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f << indent << "value<" << arg.second.size() << "> " << arg.first << ";\n";
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dec_indent();
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f << indent << "} formatter;\n";
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f << indent << "formatter.performer = performer;\n";
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for (auto arg : fmt_args) {
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f << indent << "formatter." << arg.first << " = ";
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dump_sigspec_rhs(arg.second);
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f << ";\n";
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}
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f << indent << "if (performer) {\n";
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inc_indent();
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f << indent << "static const metadata_map attributes = ";
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dump_metadata_map(cell->attributes);
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f << ";\n";
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f << indent << "performer->on_print(formatter, attributes);\n";
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dec_indent();
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f << indent << "} else {\n";
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inc_indent();
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f << indent << print_output << " << formatter();\n";
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dec_indent();
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f << indent << "}\n";
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dec_indent();
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f << indent << "}\n";
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}
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void dump_effect(const RTLIL::Cell *cell)
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{
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Fmt fmt;
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fmt.parse_rtlil(cell);
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f << indent << "if (";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << ") {\n";
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inc_indent();
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dict<std::string, RTLIL::SigSpec> fmt_args;
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f << indent << "struct : public lazy_fmt {\n";
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inc_indent();
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f << indent << "std::string operator() () const override {\n";
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inc_indent();
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fmt.emit_cxxrtl(f, indent, [&](const RTLIL::SigSpec &sig) {
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if (sig.size() == 0)
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f << "value<0>()";
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else {
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std::string arg_name = "arg" + std::to_string(fmt_args.size());
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fmt_args[arg_name] = sig;
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f << arg_name;
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}
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}, "performer");
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dec_indent();
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f << indent << "}\n";
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f << indent << "struct performer *performer;\n";
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for (auto arg : fmt_args)
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f << indent << "value<" << arg.second.size() << "> " << arg.first << ";\n";
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dec_indent();
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f << indent << "} formatter;\n";
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f << indent << "formatter.performer = performer;\n";
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for (auto arg : fmt_args) {
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f << indent << "formatter." << arg.first << " = ";
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dump_sigspec_rhs(arg.second);
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f << ";\n";
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}
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if (cell->hasPort(ID::A)) {
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f << indent << "bool condition = (bool)";
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dump_sigspec_rhs(cell->getPort(ID::A));
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f << ";\n";
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}
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f << indent << "if (performer) {\n";
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inc_indent();
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f << indent << "static const metadata_map attributes = ";
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dump_metadata_map(cell->attributes);
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f << ";\n";
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if (cell->type == ID($print)) {
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f << indent << "performer->on_print(formatter, attributes);\n";
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} else if (cell->type == ID($check)) {
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std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
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f << indent << "performer->on_check(";
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if (flavor == "assert")
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f << "flavor::ASSERT";
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else if (flavor == "assume")
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f << "flavor::ASSUME";
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else if (flavor == "live")
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f << "flavor::ASSERT_EVENTUALLY";
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else if (flavor == "fair")
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f << "flavor::ASSUME_EVENTUALLY";
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else if (flavor == "cover")
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f << "flavor::COVER";
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else log_assert(false);
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f << ", condition, formatter, attributes);\n";
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} else log_assert(false);
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dec_indent();
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f << indent << "} else {\n";
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inc_indent();
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if (cell->type == ID($print)) {
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f << indent << print_output << " << formatter();\n";
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} else if (cell->type == ID($check)) {
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std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
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if (flavor == "assert" || flavor == "assume") {
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f << indent << "if (!condition) {\n";
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inc_indent();
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f << indent << "std::cerr << formatter();\n";
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dec_indent();
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f << indent << "}\n";
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f << indent << "CXXRTL_ASSERT(condition && \"Check failed\");\n";
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}
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} else log_assert(false);
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dec_indent();
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f << indent << "}\n";
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dec_indent();
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f << indent << "}\n";
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}
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void dump_cell_eval(const RTLIL::Cell *cell, bool for_debug = false)
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{
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std::vector<const RTLIL::Cell*> inlined_cells;
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@ -1322,30 +1367,34 @@ struct CxxrtlWorker {
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f << " = ";
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dump_cell_expr(cell, for_debug);
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f << ";\n";
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// $print cell
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} else if (cell->type == ID($print)) {
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// Effectful cells
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} else if (is_effectful_cell(cell->type)) {
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log_assert(!for_debug);
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// Sync $print cells are grouped into PRINT_SYNC nodes in the FlowGraph.
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// Sync effectful cells are grouped into EFFECT_SYNC nodes in the FlowGraph.
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log_assert(!cell->getParam(ID::TRG_ENABLE).as_bool() || (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0));
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if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async $print cell
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f << indent << "auto " << mangle(cell) << "_curr = ";
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if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async effectful cell
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f << indent << "auto " << mangle(cell) << "_next = ";
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dump_sigspec_rhs(cell->getPort(ID::EN));
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f << ".concat(";
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dump_sigspec_rhs(cell->getPort(ID::ARGS));
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if (cell->type == ID($print))
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dump_sigspec_rhs(cell->getPort(ID::ARGS));
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else if (cell->type == ID($check))
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dump_sigspec_rhs(cell->getPort(ID::A));
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else log_assert(false);
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f << ").val();\n";
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f << indent << "if (" << mangle(cell) << " != " << mangle(cell) << "_curr) {\n";
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f << indent << "if (" << mangle(cell) << " != " << mangle(cell) << "_next) {\n";
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inc_indent();
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dump_print(cell);
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f << indent << mangle(cell) << " = " << mangle(cell) << "_curr;\n";
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dump_effect(cell);
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f << indent << mangle(cell) << " = " << mangle(cell) << "_next;\n";
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dec_indent();
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f << indent << "}\n";
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} else { // initial $print cell
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} else { // initial effectful cell
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f << indent << "if (!" << mangle(cell) << ") {\n";
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inc_indent();
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dump_print(cell);
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dump_effect(cell);
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f << indent << mangle(cell) << " = value<1>{1u};\n";
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dec_indent();
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f << indent << "}\n";
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@ -1728,6 +1777,47 @@ struct CxxrtlWorker {
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}
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}
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void dump_cell_effect_sync(std::vector<const RTLIL::Cell*> &cells)
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{
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log_assert(!cells.empty());
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const auto &trg = cells[0]->getPort(ID::TRG);
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const auto &trg_polarity = cells[0]->getParam(ID::TRG_POLARITY);
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f << indent << "if (";
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for (int i = 0; i < trg.size(); i++) {
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RTLIL::SigBit trg_bit = trg[i];
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trg_bit = sigmaps[trg_bit.wire->module](trg_bit);
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log_assert(trg_bit.wire);
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if (i != 0)
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f << " || ";
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if (trg_polarity[i] == State::S1)
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f << "posedge_";
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else
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f << "negedge_";
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f << mangle(trg_bit);
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}
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f << ") {\n";
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inc_indent();
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std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
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return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int();
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});
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for (auto cell : cells) {
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log_assert(cell->getParam(ID::TRG_ENABLE).as_bool());
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log_assert(cell->getPort(ID::TRG) == trg);
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log_assert(cell->getParam(ID::TRG_POLARITY) == trg_polarity);
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std::vector<const RTLIL::Cell*> inlined_cells;
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collect_cell_eval(cell, /*for_debug=*/false, inlined_cells);
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dump_inlined_cells(inlined_cells);
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dump_effect(cell);
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}
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dec_indent();
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f << indent << "}\n";
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}
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void dump_mem_rdport(const Mem *mem, int portidx, bool for_debug = false)
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{
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auto &port = mem->rd_ports[portidx];
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@ -2047,11 +2137,10 @@ struct CxxrtlWorker {
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}
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}
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for (auto cell : module->cells()) {
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// Certain $print cells have additional state, which must be reset as well.
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if (cell->type == ID($print) && !cell->getParam(ID::TRG_ENABLE).as_bool())
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f << indent << mangle(cell) << " = value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << ">();\n";
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if (cell->type == ID($print) && cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
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f << indent << mangle(cell) << " = value<1>();\n";
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// Async and initial effectful cells have additional state, which must be reset as well.
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if (is_effectful_cell(cell->type))
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if (!cell->getParam(ID::TRG_ENABLE).as_bool() || cell->getParam(ID::TRG_WIDTH).as_int() == 0)
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f << indent << mangle(cell) << " = {};\n";
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if (is_internal_cell(cell->type))
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continue;
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f << indent << mangle(cell);
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@ -2099,8 +2188,8 @@ struct CxxrtlWorker {
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case FlowGraph::Node::Type::CELL_EVAL:
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dump_cell_eval(node.cell);
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break;
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case FlowGraph::Node::Type::PRINT_SYNC:
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dump_sync_print(node.print_sync_cells);
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case FlowGraph::Node::Type::EFFECT_SYNC:
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dump_cell_effect_sync(node.cells);
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break;
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case FlowGraph::Node::Type::PROCESS_CASE:
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dump_process_case(node.process);
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@ -2481,11 +2570,15 @@ struct CxxrtlWorker {
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f << "\n";
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bool has_cells = false;
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for (auto cell : module->cells()) {
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// Certain $print cells have additional state, which requires storage.
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if (cell->type == ID($print) && !cell->getParam(ID::TRG_ENABLE).as_bool())
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f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n";
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if (cell->type == ID($print) && cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
|
||||
f << indent << "value<1> " << mangle(cell) << ";\n";
|
||||
// Async and initial effectful cells have additional state, which requires storage.
|
||||
if (is_effectful_cell(cell->type)) {
|
||||
if (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)
|
||||
f << indent << "value<1> " << mangle(cell) << ";\n"; // async initial cell
|
||||
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($print))
|
||||
f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n"; // {EN, ARGS}
|
||||
if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($check))
|
||||
f << indent << "value<2> " << mangle(cell) << ";\n"; // {EN, A}
|
||||
}
|
||||
if (is_internal_cell(cell->type))
|
||||
continue;
|
||||
dump_attrs(cell);
|
||||
|
|
@ -2803,8 +2896,8 @@ struct CxxrtlWorker {
|
|||
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
|
||||
}
|
||||
|
||||
// $print cells may be triggered on posedge/negedge events.
|
||||
if (cell->type == ID($print) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
|
||||
// Effectful cells may be triggered on posedge/negedge events.
|
||||
if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
|
||||
for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) {
|
||||
RTLIL::SigBit trg = cell->getPort(ID::TRG).extract(i, 1);
|
||||
if (is_valid_clock(trg))
|
||||
|
|
@ -2945,10 +3038,12 @@ struct CxxrtlWorker {
|
|||
// Discover nodes reachable from primary outputs (i.e. members) and collect reachable wire users.
|
||||
pool<FlowGraph::Node*, hash_ptr_ops> worklist;
|
||||
for (auto node : flow.nodes) {
|
||||
if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type))
|
||||
worklist.insert(node); // node has effects
|
||||
else if (node->type == FlowGraph::Node::Type::PRINT_SYNC)
|
||||
worklist.insert(node); // node is sync $print
|
||||
if (node->type == FlowGraph::Node::Type::CELL_EVAL && !is_internal_cell(node->cell->type))
|
||||
worklist.insert(node); // node evaluates a submodule
|
||||
else if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type))
|
||||
worklist.insert(node); // node has async effects
|
||||
else if (node->type == FlowGraph::Node::Type::EFFECT_SYNC)
|
||||
worklist.insert(node); // node has sync effects
|
||||
else if (node->type == FlowGraph::Node::Type::MEM_WRPORTS)
|
||||
worklist.insert(node); // node is memory write
|
||||
else if (node->type == FlowGraph::Node::Type::PROCESS_SYNC && is_memwr_process(node->process))
|
||||
|
|
@ -3005,21 +3100,21 @@ struct CxxrtlWorker {
|
|||
}
|
||||
|
||||
// Emit reachable nodes in eval().
|
||||
// Accumulate sync $print cells per trigger condition.
|
||||
dict<std::pair<RTLIL::SigSpec, RTLIL::Const>, std::vector<const RTLIL::Cell*>> sync_print_cells;
|
||||
// Accumulate sync effectful cells per trigger condition.
|
||||
dict<std::pair<RTLIL::SigSpec, RTLIL::Const>, std::vector<const RTLIL::Cell*>> effect_sync_cells;
|
||||
for (auto node : node_order)
|
||||
if (live_nodes[node]) {
|
||||
if (node->type == FlowGraph::Node::Type::CELL_EVAL &&
|
||||
node->cell->type == ID($print) &&
|
||||
is_effectful_cell(node->cell->type) &&
|
||||
node->cell->getParam(ID::TRG_ENABLE).as_bool() &&
|
||||
node->cell->getParam(ID::TRG_WIDTH).as_int() != 0)
|
||||
sync_print_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
|
||||
effect_sync_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
|
||||
else
|
||||
schedule[module].push_back(*node);
|
||||
}
|
||||
|
||||
for (auto &it : sync_print_cells) {
|
||||
auto node = flow.add_print_sync_node(it.second);
|
||||
for (auto &it : effect_sync_cells) {
|
||||
auto node = flow.add_effect_sync_node(it.second);
|
||||
schedule[module].push_back(*node);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue