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Fixed bug in "read_verilog -ignore_redef"

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This commit is contained in:
Clifford Wolf 2014-08-15 01:53:22 +02:00
parent 978a933b6a
commit c7afbd9d8e
1 changed files with 1 additions and 1 deletions
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2
frontends/ast/ast.cc
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@ -947,7 +947,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
if (!ignore_redef) if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n", log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
log_error("Ignoring re-definition of module `%s' at %s:%d!\n", log("Ignoring re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue; continue;
} }