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machxo2: Add passing fsm, mux, and shifter tests.

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William D. Jones 2020-11-26 22:30:48 -05:00 • committed by Marcelina Kościelnicka
parent 453904dd00
commit c7aaa88f58
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tests/arch/machxo2/shifter.ys Normal file
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read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 8 t:FACADE_FF
select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D