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machxo2: Add passing fsm, mux, and shifter tests.

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William D. Jones 2020-11-26 22:30:48 -05:00 • committed by Marcelina Kościelnicka
parent 453904dd00
commit c7aaa88f58
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tests/arch/machxo2/fsm.ys Normal file
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read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2
miter -equiv -make_assert -flatten gold gate miter
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-max 16 t:LUT4
select -assert-count 6 t:FACADE_FF
select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D