3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 20:21:25 +00:00

mem2reg: tolerate out of bounds constant accesses

This brings the mem2reg behavior in line with the nomem2reg behavior.
This commit is contained in:
Zachary Snow 2021-05-26 18:22:31 -04:00 committed by Zachary Snow
parent d9f11bb7a6
commit c79fbfe0a1
4 changed files with 94 additions and 5 deletions

View file

@ -0,0 +1,19 @@
module top(
input clk,
input wire [1:0] sel,
input wire [7:0] base,
output reg [7:0] line
);
reg [0:7] mem [0:2];
generate
genvar i;
for (i = 0; i < 4; i = i + 1) begin : gen
always @(posedge clk)
mem[i] <= i == 0 ? base : mem[i - 1] + 1;
end
endgenerate
always @(posedge clk)
line = mem[sel];
endmodule