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Merge pull request #25 from alaindargelas/fix_bus_reconstruct_assert

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Fix bus reconstruct assert
This commit is contained in:
Akash Levy 2024-11-19 10:42:07 -08:00 • committed by GitHub
commit c768589b5d
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GPG key ID: B5690EEEBB952194
3 changed files with 88 additions and 19 deletions
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99
passes/cmds/reconstructbusses.cc
View file

@ -54,6 +54,9 @@ struct ReconstructBusses : public ScriptPass {
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (wire->name[0] == '$') // Skip internal wires if (wire->name[0] == '$') // Skip internal wires
continue; continue;
if ((!wire->port_input) && (!wire->port_output)) {
continue;
}
std::string prefix = wire->name.str(); std::string prefix = wire->name.str();
if (prefix.empty()) if (prefix.empty())
@ -100,6 +103,10 @@ struct ReconstructBusses : public ScriptPass {
} }
} }
log("Found %ld groups\n", wire_groups.size()); log("Found %ld groups\n", wire_groups.size());
if (wire_groups.size() == 0) {
std::cout << "No busses to reconstruct. Done." << std::endl;
continue;
}
log("Creating busses\n"); log("Creating busses\n");
log_flush(); log_flush();
std::map<std::string, RTLIL::Wire *> wirenames_to_remove; std::map<std::string, RTLIL::Wire *> wirenames_to_remove;
@ -154,9 +161,22 @@ struct ReconstructBusses : public ScriptPass {
if (lhsIndex >= 0) { if (lhsIndex >= 0) {
// Create a new connection sigspec that matches the previous // Create a new connection sigspec that matches the previous
// bit index // bit index
RTLIL::SigSpec bit = RTLIL::SigSpec(itr_lhs->second, lhsIndex, 1); if (lhsIndex < itr_lhs->second->width) {
new_sig.append(bit); RTLIL::SigSpec bit = RTLIL::SigSpec(itr_lhs->second, lhsIndex, 1);
modified = true; new_sig.append(bit);
modified = true;
} else {
log_warning("Attempting to reconnect cell %s, port: %s of size %d with "
"out-of-bound index %d\n",
cell->name.c_str(), conn.first.c_str(), itr_lhs->second->width,
lhsIndex);
for (RTLIL::Wire *w : wires_to_remove) {
if (strcmp(w->name.c_str(), itr_lhs->second->name.c_str()) == 0) {
wires_to_remove.erase(w);
break;
}
}
}
} else { } else {
new_sig.append(chunk); new_sig.append(chunk);
modified = true; modified = true;
@ -203,27 +223,73 @@ struct ReconstructBusses : public ScriptPass {
std::map<std::string, RTLIL::Wire *>::iterator itr_rhs = wirenames_to_remove.find(conn_rhs_s); std::map<std::string, RTLIL::Wire *>::iterator itr_rhs = wirenames_to_remove.find(conn_rhs_s);
if (itr_lhs != wirenames_to_remove.end() || itr_rhs != wirenames_to_remove.end()) { if (itr_lhs != wirenames_to_remove.end() || itr_rhs != wirenames_to_remove.end()) {
if (lhsIndex >= 0) { if (lhsIndex >= 0) {
RTLIL::SigSpec lbit;
// Create the LHS sigspec of the desired bit // Create the LHS sigspec of the desired bit
RTLIL::SigSpec lbit = RTLIL::SigSpec(itr_lhs->second, lhsIndex, 1); if (lhsIndex < itr_lhs->second->width) {
lbit = RTLIL::SigSpec(itr_lhs->second, lhsIndex, 1);
} else {
lbit = itr_lhs->second;
log_warning("Attempting to reconnect signal %s, of "
"size %d with out-of-bound index %d\n",
conn_lhs_s.c_str(),
itr_lhs->second->width, lhsIndex);
for (RTLIL::Wire *w : wires_to_remove) {
if (strcmp(w->name.c_str(),conn_lhs_s.c_str()) == 0) {
wires_to_remove.erase(w);
break;
}
}
}
if (sub_rhs.size() > 1) { if (sub_rhs.size() > 1) {
// If RHS has width > 1, replace with the bitblasted RHS // If RHS has width > 1, replace with the bitblasted RHS
// corresponding to the connected bit // corresponding to the connected bit
RTLIL::SigSpec rhs_bit = RTLIL::SigSpec(sub_rhs.wire, lhsIndex, 1); if (lhsIndex < sub_rhs.wire->width) {
// And connect it RTLIL::SigSpec rhs_bit = RTLIL::SigSpec(sub_rhs.wire, lhsIndex, 1);
module->connect(lbit, rhs_bit); // And connect it
module->connect(lbit, rhs_bit);
} else {
log_warning("Attempting to reconnect signal %s, of "
"size %d with out-of-bound index %d\n",
conn_rhs_s.c_str(),
sub_rhs.wire->width, lhsIndex);
for (RTLIL::Wire *w : wires_to_remove) {
if (strcmp(w->name.c_str(), conn_rhs_s.c_str()) == 0) {
wires_to_remove.erase(w);
break;
}
}
}
} else { } else {
// Else, directly connect // Else, directly connect
if (rhsIndex >= 0) { if (rhsIndex >= 0) {
RTLIL::SigSpec rbit = RTLIL::SigSpec(itr_rhs->second, rhsIndex, 1); if (rhsIndex < itr_rhs->second->width) {
module->connect(lbit, rbit); RTLIL::SigSpec rbit =
RTLIL::SigSpec(itr_rhs->second, rhsIndex, 1);
module->connect(lbit, rbit);
} else {
log_warning("Attempting to reconnect signal %s, of "
"size %d with out-of-bound index %d\n",
conn_rhs_s.c_str(),
itr_rhs->second->width, rhsIndex);
for (RTLIL::Wire *w : wires_to_remove) {
if (strcmp(w->name.c_str(), conn_rhs_s.c_str()) == 0) {
wires_to_remove.erase(w);
break;
}
}
}
} else { } else {
module->connect(lbit, sub_rhs); module->connect(lbit, sub_rhs);
} }
} }
} else { } else {
// Else, directly connect // LHS is not a bus
RTLIL::SigSpec bit = RTLIL::SigSpec(itr_lhs->second, 0, 1); if (itr_rhs->second->width > 1) {
module->connect(bit, sub_rhs); RTLIL::SigSpec rhs_bit = RTLIL::SigSpec(itr_rhs->second, 0, 1);
module->connect(sub_lhs, rhs_bit);
} else {
module->connect(sub_lhs, sub_rhs);
}
} }
} }
} }
@ -234,10 +300,15 @@ struct ReconstructBusses : public ScriptPass {
} }
if (debug) if (debug)
run_pass("write_rtlil post_reconnect_top.rtlil"); run_pass("write_rtlil post_reconnect_top.rtlil");
// Remove old wires // Remove old bit blasted wires
// Cleans the dangling connections too // Cleans the dangling connections too
log("Removing old wires\n"); log("Removing bit blasted wires\n");
log_flush(); log_flush();
if (debug) {
for (RTLIL::Wire *w : wires_to_remove) {
std::cout << " " << w->name.c_str() << std::endl;
}
}
module->remove(wires_to_remove); module->remove(wires_to_remove);
// Update module port list // Update module port list
log("Re-creating ports\n"); log("Re-creating ports\n");

2
passes/cmds/splitnetlist.cc
View file

@ -266,7 +266,7 @@ struct SplitNetlist : public ScriptPass {
} }
// Execute the submod command // Execute the submod command
Pass::call(design, "submod -copy"); Pass::call(design, "submod");
// Remove buffers introduced by bufnorm // Remove buffers introduced by bufnorm
Pass::call(design, "techmap -D SIMLIB_NOCHECKS -map +/simlib.v t:$buf"); Pass::call(design, "techmap -D SIMLIB_NOCHECKS -map +/simlib.v t:$buf");

6
passes/cmds/stat.cc
View file

@ -355,9 +355,7 @@ struct statdata_t
log(" \"num_memory_bits\": %u,\n", num_memory_bits); log(" \"num_memory_bits\": %u,\n", num_memory_bits);
log(" \"num_processes\": %u,\n", num_processes); log(" \"num_processes\": %u,\n", num_processes);
log(" \"num_cells\": %u,\n", num_cells); log(" \"num_cells\": %u,\n", num_cells);
if (area != 0) { log(" \"area\": %f,\n", area);
log(" \"area\": %f,\n", area);
}
log(" \"num_cells_by_type\": {\n"); log(" \"num_cells_by_type\": {\n");
bool first_line = true; bool first_line = true;
for (auto &it : num_cells_by_type) for (auto &it : num_cells_by_type)
@ -507,7 +505,7 @@ void read_libjson_cellarea(dict<IdString, cell_area_t> &cell_area, string libert
if (f == NULL) if (f == NULL)
log_cmd_error("Can't open input file `%s' for reading: %s\n", liberty_file.c_str(), strerror(errno)); log_cmd_error("Can't open input file `%s' for reading: %s\n", liberty_file.c_str(), strerror(errno));
nlohmann::json data = nlohmann::json::parse(*f); nlohmann::json data = nlohmann::json::parse(*f);
nlohmann::json library = data["library"]; nlohmann::json library = data["library"];
if (library.contains("groups")) { if (library.contains("groups")) {
nlohmann::json groups = library["groups"]; nlohmann::json groups = library["groups"];