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modtools: fix database sanity on wire name swap

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This commit is contained in:
Emil J. Tywoniak 2026-02-18 21:20:13 +01:00
parent 62f19cb3a9
commit c75d80905a
1 changed files with 17 additions and 1 deletions
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18
kernel/modtools.h
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@ -28,6 +28,22 @@ YOSYS_NAMESPACE_BEGIN
struct ModIndex : public RTLIL::Monitor struct ModIndex : public RTLIL::Monitor
{ {
struct PointerOrderedSigBit : public RTLIL::SigBit {
PointerOrderedSigBit(SigBit s) {
wire = s.wire;
if (wire)
offset = s.offset;
else
data = s.data;
}
inline bool operator<(const RTLIL::SigBit &other) const {
if (wire == other.wire)
return wire ? (offset < other.offset) : (data < other.data);
if (wire != nullptr && other.wire != nullptr)
return wire < other.wire; // look here
return (wire != nullptr) < (other.wire != nullptr);
}
};
struct PortInfo { struct PortInfo {
RTLIL::Cell* cell; RTLIL::Cell* cell;
RTLIL::IdString port; RTLIL::IdString port;
@ -77,7 +93,7 @@ struct ModIndex : public RTLIL::Monitor
SigMap sigmap; SigMap sigmap;
RTLIL::Module *module; RTLIL::Module *module;
std::map<RTLIL::SigBit, SigBitInfo> database; std::map<PointerOrderedSigBit, SigBitInfo> database;
int auto_reload_counter; int auto_reload_counter;
bool auto_reload_module; bool auto_reload_module;