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https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
WIP
This commit is contained in:
Eddie Hung
parent
941365b4bb
commit
c748391730
1 changed files with 68 additions and 14 deletions
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@ -61,6 +61,8 @@ struct XAigerWriter
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dict<SigBit, int> init_inputs;
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int initstate_ff = 0;
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vector<Cell*> box_list;
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int mkgate(int a0, int a1)
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{
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aig_m++, aig_a++;
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@ -211,7 +213,7 @@ struct XAigerWriter
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}
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for (const auto &c : cell->connections()) {
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if (c.second.is_fully_const()) continue;
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/*if (c.second.is_fully_const()) continue;*/
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for (auto b : c.second.bits()) {
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Wire *w = b.wire;
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if (!w) continue;
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@ -219,30 +221,32 @@ struct XAigerWriter
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auto is_output = cell->output(c.first);
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log_assert(is_input || is_output);
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if (is_input) {
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if (!w->port_input) {
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/*if (!w->port_input)*/ {
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SigBit I = sigmap(b);
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if (I != b)
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alias_map[b] = I;
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if (!output_bits.count(b))
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/*if (!output_bits.count(b))*/
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co_bits.insert(b);
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}
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}
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if (is_output) {
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SigBit O = sigmap(b);
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if (!input_bits.count(O))
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/*if (!input_bits.count(O))*/
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ci_bits.insert(O);
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}
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}
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if (!type_map.count(cell->type))
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type_map[cell->type] = type_map.size()+1;
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}
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//log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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box_list.emplace_back(cell);
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log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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for (auto bit : input_bits) {
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RTLIL::Wire *wire = bit.wire;
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// If encountering an inout port, then create a new wire with $inout.out
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// suffix, make it a CO driven by the existing inout, and inherit existing
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// suffix, make it a PO driven by the existing inout, and inherit existing
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// inout's drivers
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if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) {
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RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out");
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@ -256,19 +260,19 @@ struct XAigerWriter
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and_map[new_bit] = and_map.at(bit);
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else if (alias_map.count(bit))
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alias_map[new_bit] = alias_map.at(bit);
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co_bits.insert(new_bit);
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output_bits.insert(new_bit);
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}
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}
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// Do some CI/CO post-processing:
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// Erase all POs and COs that are undriven
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for (auto bit : undriven_bits) {
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co_bits.erase(bit);
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//co_bits.erase(bit);
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output_bits.erase(bit);
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}
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// Erase all CIs that are also COs
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for (auto bit : co_bits)
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ci_bits.erase(bit);
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//for (auto bit : co_bits)
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// ci_bits.erase(bit);
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// CIs cannot be undriven
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for (auto bit : ci_bits)
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undriven_bits.erase(bit);
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@ -491,6 +495,7 @@ struct XAigerWriter
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if (output_bits.count(b) || co_bits.count(b)) {
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int o = ordered_outputs.at(b);
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if (output_seen && output_bits.count(b))
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output_seen = !miter_mode;
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if (GetSize(wire) != 1)
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symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
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@ -532,7 +537,52 @@ struct XAigerWriter
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}
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}
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f << stringf("c\nGenerated by %s\n", yosys_version_str);
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f << "c";
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std::stringstream h_buffer;
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auto write_h_buffer = [&h_buffer](int i32) {
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// TODO: Don't assume we're on little endian
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#ifdef _WIN32
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int i32_be = _byteswap_ulong(i32);
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#else
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int i32_be = __builtin_bswap32(i32);
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#endif
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h_buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
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};
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int num_outputs = output_bits.size();
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if (omode && num_outputs == 0)
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num_outputs = 1;
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write_h_buffer(1);
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write_h_buffer(input_bits.size() + ci_bits.size());
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write_h_buffer(num_outputs + co_bits.size());
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write_h_buffer(input_bits.size());
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write_h_buffer(num_outputs);
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write_h_buffer(box_list.size());
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int box_id = 0;
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for (auto cell : box_list) {
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int box_inputs = 0, box_outputs = 0;
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for (const auto &c : cell->connections())
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if (cell->input(c.first))
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box_inputs += c.second.size();
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else
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box_outputs += c.second.size();
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write_h_buffer(box_inputs);
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write_h_buffer(box_outputs);
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write_h_buffer(box_id++);
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write_h_buffer(0 /* OldBoxNum */);
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}
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std::string h_buffer_str = h_buffer.str();
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// TODO: Don't assume we're on little endian
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#ifdef _WIN32
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int h_buffer_size_be = _byteswap_ulong(h_buffer_str.size());
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#else
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int h_buffer_size_be = __builtin_bswap32(h_buffer_str.size());
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#endif
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f << "h";
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f.write(reinterpret_cast<const char*>(&h_buffer_size_be), sizeof(h_buffer_size_be));
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f.write(h_buffer_str.data(), h_buffer_str.size());
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f << stringf("Generated by %s\n", yosys_version_str);
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}
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void write_map(std::ostream &f, bool verbose_map, bool omode)
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@ -557,6 +607,10 @@ struct XAigerWriter
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int a = aig_map.at(sig[i]);
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log_assert((a & 1) == 0);
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input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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// Only continue if this input is not a CO,
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// otherwise write as CO below
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if (!co_bits.count(b))
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continue;
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}
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@ -606,7 +660,7 @@ struct XAigerWriter
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f << it.second;
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log_assert(output_lines.size() == output_bits.size() + co_bits.size());
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if (omode && output_lines.empty())
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f << "output 0 0 __dummy_o__\n";
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f << "output " << output_lines.size() << " 0 __dummy_o__\n";
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latch_lines.sort();
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for (auto &it : latch_lines)
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