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https://github.com/YosysHQ/yosys
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gowin: Use dfflegalize.
This commit is contained in:
Marcelina Kościelnicka
parent
09ecb9b2cf
commit
c73ebeb90e
4 changed files with 49 additions and 158 deletions
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@ -3,228 +3,123 @@
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//value regardless. The parameter is ignored.
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// DFFN D Flip-Flop with Negative-Edge Clock
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module \$_DFF_N_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
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generate
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if (_TECHMAP_WIREINIT_Q_ === 1'b1)
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DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
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else
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module \$_DFF_N_ (input D, C, output Q);
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DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
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endgenerate
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFF D Flip-Flop
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module \$_DFF_P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, output Q);
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generate
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if (_TECHMAP_WIREINIT_Q_ === 1'b1)
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DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(1'b0));
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else
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module \$_DFF_P_ (input D, C, output Q);
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DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
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endgenerate
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFE D Flip-Flop with Clock Enable
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module \$_DFFE_PP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
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generate
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if (_TECHMAP_WIREINIT_Q_ === 1'b1)
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DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
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else
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module \$_DFFE_PP_ (input D, C, E, output Q);
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DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
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endgenerate
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_PN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
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generate
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if (_TECHMAP_WIREINIT_Q_ === 1'b1)
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DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
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else
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DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
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endgenerate
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
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module \$_DFFE_NP_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
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generate
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if (_TECHMAP_WIREINIT_Q_ === 1'b1)
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DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E), .SET(1'b0));
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else
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module \$_DFFE_NP_ (input D, C, E, output Q);
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DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
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endgenerate
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, output Q);
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generate
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if (_TECHMAP_WIREINIT_Q_ === 1'b1)
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DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E), .SET(1'b0));
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else
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DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E));
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endgenerate
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFR D Flip-Flop with Synchronous Reset
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module \$_SDFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_SDFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_SDFF_PP0_ (input D, C, R, output Q);
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DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
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module \$_SDFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_SDFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_SDFF_NP0_ (input D, C, R, output Q);
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DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
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module \$_SDFFE_PN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_SDFFE_PP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_SDFFE_PP0P_ (input D, C, R, E, output Q);
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DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
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module \$_SDFFE_NN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_SDFFE_NP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_SDFFE_NP0P_ (input D, C, R, E, output Q);
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DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFS D Flip-Flop with Synchronous Set
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module \$_SDFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_SDFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_SDFF_PP1_ (input D, C, R, output Q);
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DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
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module \$_SDFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_SDFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_SDFF_NP1_ (input D, C, R, output Q);
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DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
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module \$_SDFFE_PN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_SDFFE_PP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_SDFFE_PP1P_ (input D, C, R, E, output Q);
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DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
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module \$_SDFFE_NN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_SDFFE_NP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_SDFFE_NP1P_ (input D, C, R, E, output Q);
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DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFP D Flip-Flop with Asynchronous Preset
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module \$_DFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_DFF_PP1_ (input D, C, R, output Q);
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DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_DFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
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module \$_DFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_DFF_NP1_ (input D, C, R, output Q);
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DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_DFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFC D Flip-Flop with Asynchronous Clear
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module \$_DFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_DFF_PP0_ (input D, C, R, output Q);
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DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_DFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
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module \$_DFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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module \$_DFF_NP0_ (input D, C, R, output Q);
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DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
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DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
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module \$_DFFE_PP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_DFFE_PP1P_ (input D, C, R, E, output Q);
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DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_DFFE_PN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
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module \$_DFFE_NP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_DFFE_NP1P_ (input D, C, R, E, output Q);
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DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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endmodule
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module \$_DFFE_NN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
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module \$_DFFE_PP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_DFFE_PP0P_ (input D, C, R, E, output Q);
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DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_DFFE_PN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
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module \$_DFFE_NP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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module \$_DFFE_NP0P_ (input D, C, R, E, output Q);
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DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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endmodule
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module \$_DFFE_NN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
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DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
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wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
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wire _TECHMAP_REMOVEINIT_Q_ = 1;
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endmodule
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@ -223,6 +223,7 @@ struct SynthGowinPass : public ScriptPass
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run("opt_clean");
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if (!nodffe)
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run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
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run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r");
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run("techmap -map +/gowin/cells_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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5
tests/arch/gowin/init-error.ys
Normal file
5
tests/arch/gowin/init-error.ys
Normal file
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@ -0,0 +1,5 @@
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read_verilog init.v
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chparam -set INIT 0 myDFF*P*
|
||||
hierarchy -top myDFFP
|
||||
logger -expect error "unsupported initial value and async reset value combination" 1
|
||||
synth_gowin
|
||||
|
|
@ -35,10 +35,10 @@ design -load read
|
|||
# these should synth to a flop with reset
|
||||
chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE
|
||||
|
||||
# async should give a warning
|
||||
# async would give an error
|
||||
# sync should synth to a mux
|
||||
chparam -set INIT 0 myDFF*S* myDFF*P*
|
||||
chparam -set INIT 1 myDFF*R* myDFF*C*
|
||||
chparam -set INIT 0 myDFF*S*
|
||||
chparam -set INIT 1 myDFF*R*
|
||||
|
||||
proc
|
||||
flatten
|
||||
|
|
@ -66,13 +66,3 @@ select -assert-count 0 t:DFFRE
|
|||
select -assert-count 2 t:DFFS
|
||||
select -assert-count 2 t:DFFSE
|
||||
select -assert-count 12 t:LUT2
|
||||
|
||||
# Remove all whiteboxes so we don't inadvertently
|
||||
# count init attributes inside them
|
||||
# Should be superseded by https://github.com/YosysHQ/yosys/pull/1949
|
||||
delete A:whitebox=1
|
||||
|
||||
# check the expected leftover init values
|
||||
# this would happen if your reset value is not the initial value
|
||||
# which would be weird
|
||||
select -assert-count 8 a:init
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue