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Fixed build of verific bindings

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This commit is contained in:
Clifford Wolf 2014-07-31 16:45:23 +02:00
parent cdae8abe16
commit c6fd82c70b
1 changed files with 11 additions and 11 deletions
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22
frontends/verific/verific.cc
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@ -693,9 +693,9 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
cell->parameters["\\TRANSPARENT"] = false; cell->parameters["\\TRANSPARENT"] = false;
cell->parameters["\\ABITS"] = SIZE(addr); cell->parameters["\\ABITS"] = SIZE(addr);
cell->parameters["\\WIDTH"] = SIZE(data); cell->parameters["\\WIDTH"] = SIZE(data);
cell->set("\\CLK", RTLIL::State::S0); cell->setPort("\\CLK", RTLIL::State::S0);
cell->set("\\ADDR", addr); cell->setPort("\\ADDR", addr);
cell->set("\\DATA", data); cell->setPort("\\DATA", data);
continue; continue;
} }
@ -715,14 +715,14 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
cell->parameters["\\PRIORITY"] = 0; cell->parameters["\\PRIORITY"] = 0;
cell->parameters["\\ABITS"] = SIZE(addr); cell->parameters["\\ABITS"] = SIZE(addr);
cell->parameters["\\WIDTH"] = SIZE(data); cell->parameters["\\WIDTH"] = SIZE(data);
cell->set("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(SIZE(data))); cell->setPort("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(SIZE(data)));
cell->set("\\CLK", RTLIL::State::S0); cell->setPort("\\CLK", RTLIL::State::S0);
cell->set("\\ADDR", addr); cell->setPort("\\ADDR", addr);
cell->set("\\DATA", data); cell->setPort("\\DATA", data);
if (inst->Type() == OPER_CLOCKED_WRITE_PORT) { if (inst->Type() == OPER_CLOCKED_WRITE_PORT) {
cell->parameters["\\CLK_ENABLE"] = true; cell->parameters["\\CLK_ENABLE"] = true;
cell->set("\\CLK", net_map.at(inst->GetClock())); cell->setPort("\\CLK", net_map.at(inst->GetClock()));
} }
continue; continue;
} }
@ -755,15 +755,15 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
std::min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex()); std::min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
} }
RTLIL::SigSpec conn; RTLIL::SigSpec conn;
if (cell->has(RTLIL::escape_id(port_name))) if (cell->hasPort(RTLIL::escape_id(port_name)))
conn = cell->get(RTLIL::escape_id(port_name)); conn = cell->getPort(RTLIL::escape_id(port_name));
while (SIZE(conn) <= port_offset) { while (SIZE(conn) <= port_offset) {
if (pr->GetPort()->GetDir() != DIR_IN) if (pr->GetPort()->GetDir() != DIR_IN)
conn.append(module->addWire(NEW_ID, port_offset - SIZE(conn))); conn.append(module->addWire(NEW_ID, port_offset - SIZE(conn)));
conn.append(RTLIL::State::Sz); conn.append(RTLIL::State::Sz);
} }
conn.replace(port_offset, net_map.at(pr->GetNet())); conn.replace(port_offset, net_map.at(pr->GetNet()));
cell->set(RTLIL::escape_id(port_name), conn); cell->setPort(RTLIL::escape_id(port_name), conn);
} }
} }
} }