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Merge branch 'eddie/fix_sat_init' into eddie/fix1427

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This commit is contained in:
Eddie Hung 2019-10-02 18:07:38 -07:00
commit c6a55d948a
2 changed files with 24 additions and 1 deletions
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5
passes/sat/sat.cc
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@ -265,15 +265,18 @@ struct SatHelper
RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
log_assert(lhs.size() == rhs.size());
dict<RTLIL::SigBit,SigBit> seen_init;
RTLIL::SigSpec removed_bits;
for (int i = 0; i < lhs.size(); i++) {
RTLIL::SigSpec bit = lhs.extract(i, 1);
if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) {
removed_bits.append(bit);
lhs.remove(i, 1);
rhs.remove(i, 1);
i--;
}
else
seen_init[bit] = rhs[i];
}
if (removed_bits.size())

20
tests/sat/initval.ys
View file

@ -2,3 +2,23 @@ read_verilog -sv initval.v
proc;;
sat -seq 10 -prove-asserts
read_verilog <<EOT
module gold(input clk, input i, output reg [1:0] o);
initial o = 2'b10;
always @(posedge clk)
o[0] <= {i,i};
endmodule
module gate(input clk, input i, output reg [1:0] o);
initial o = 2'b10;
always @(posedge clk)
o[0] <= i;
always @*
o[1] <= o[0];
endmodule
EOT
proc
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -seq 1 -falsify -prove-asserts -show-ports miter